MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 589

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
PCI_GNT[1:2]
PCI_FRAME
PCI_IDSEL
PCI_GNT0
Signal
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 13-3. PCI Interface Signals—Detailed Signal Descriptions (continued)
I/O
I/O PCI cycle frame. Used by the current PCI master to indicate the beginning and duration of an access.
I/O PCI arbiter grants. Output signal on this PCI controller when the arbiter is enabled. Input signal when
O
O
O
I
I
I
Outputs for the bi-directional frame.
Inputs for the bi-directional frame.
the arbiter is disabled.
Note: PCI_GNT[0] is a point-to-point signal. Every master has its own bus grant signal.
Outputs for the bi-directional arbiter grants.
Inputs for the bi-directional arbiter grants.
PCI arbiter grants. Output signals on this PCI controller when the arbiter is enabled. Note that
PCI_GNT n is a point-to-point signal. Every master has its own bus grant signal.
PCI initialization device select. Used as a chip select during a PCI configuration cycle in agent mode.
This signal should be tied low in host mode.
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
State
State
State
State
State
State
Asserted—The PCI controller acting as a PCI master which is initiating a bus transaction.
Negated—If PCI_IRDY is asserted, indicates that the PCI transaction is in the final data
Asserted—Another PCI master is initiating a bus transaction.
Negated—The transaction is in the final data phase or that the bus is idle.
Asserted—The PCI controller granted control of the PCI bus to agent 0.
Negated—The PCI controller did not grant control of the PCI bus to agent 0.
Asserted—The PCI controller has been granted control of the PCI bus by an external
Negated—The PCI controller has not been granted control of the PCI bus by an external
Asserted—The PCI controller granted control of the PCI bus to agent n .
Negated—The PCI controller did not grant control of the PCI bus to agent n .
Asserted—The PCI controller is being selected as a target of a configuration read or write
Negated—The PCI controller is not being selected as a target of configuration read or
While PCI_FRAME is asserted, data transfers may continue.
phase; if PCI_IRDY is negated, indicates that the PCI bus is idle.
arbiter.
arbiter.
transactions.
write transactions.
Description
PCI Bus Interface
13-7