MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 866

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
bytes. During reception, the Ethernet controller checks for frames that are too short or too long. After the
frame ends (CRS is negated), the receive CRC field is checked and written to the data buffer. The data
length written to the last RxBD in the Ethernet frame is the length of the entire frame, which enables the
software to recognize an oversized frame condition.
Receive frames are not truncated when they exceed maximum frame bytes in the MAC’s maximum frame
register if MACCFG2[Huge Frame] is set, yet the babbling receiver error interrupt occurs
(IEVENT[BABR] is set) and RxBD[LG] is set.
After the receive frame is complete, the Ethernet controller sets RxBD[L], updates the frame status bits in
the RxBD, and clears RxBD[E]. If RxBD[I] is set, the Ethernet controller next generates an interrupt (that
can be masked) indicating that a frame was received and is in memory. The Ethernet controller then waits
for a new frame.
To interrupt reception or rearrange the receive queue, DMACTRL[GRS] must be set. If this bit is set, the
eTSEC receiver performs a graceful receive stop. The Ethernet controller stops immediately if no frames
are being received or continues receiving until the current frame either finishes or an error condition
occurs. The IEVENT[GRSC] interrupt event is signaled after the graceful receive stop operation is
completed. While in this mode the user can write to registers that are accessible to both the user and the
eTSEC hardware without fear of conflict, and finally clear IEVENT[GRSC]. After DMACTRL[GRS] is
cleared, the eTSEC scans the input data stream for the start of a new frame (preamble sequence and start
of frame delimiter), it resumes receiving, and the first valid frame received is placed in the next available
RxBD.
15.6.2.5
By default eTSEC generates a standard Ethernet preamble sequence prior to transmitting frames.
However, the user can substitute a custom preamble sequence for the purpose of controlling switching
equipment at the receiver, particularly at 100/1000Mbps speeds.; in any RMII mode only the standard
preamble can be transmitted
eTSEC normally searches for and discards the standard Ethernet preamble sequence upon receiving
frames. Part of the received preamble sequence can be optionally recovered and returned as part of the
frame data, making it visible to user software. Note however, that , and preamble cannot be recovered in
any RMII mode. Note that it is also possible for the first two bytes of custom preamble (PreOct0 and
PreOct1) to be lost in during conversion to ten-bit code groups in the PCS sub-layer. Thus is it
recommended that any custom preamble start at PreOct2.
15.6.2.5.1
To substitute a custom preamble, the user must ensure that:
15-148
•
•
•
MACCFG2[PreAm TxEN] bit is set
The first TxBD of every frame containing a custom preamble has its PRE bit set
An 8-byte custom preamble sequence appears before the Ethernet DA field in the first transmit data
buffer
Ethernet Preamble Customization
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
User-Defined Preamble Transmission
Freescale Semiconductor