MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 940

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.3.2.1
The module executes the command indicated in this register.
16-12
Offset 0x2_3140
Reset
Reset
31–24
23–16
Bits
15
14
13
12
11
10
W
W
R
R
FS2 ATDTW SUTW
31
15
0
0
ATDTW Add dTD TripWire. This is a non-EHCI bit. Used as a semaphore when a dTD is added to an active (primed)
SUTW
Name
ASPE
FS2
ITC
—
—
—
USB Command Register (USBCMD)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
14
0
0
Reserved, should be cleared.
Interrupt threshold control. The system software uses this field to set the maximum rate at which the USB
DR module will issue interrupts. ITC contains the maximum interrupt interval measured in microframes.
Valid values are shown below.
0x00 Immediate (no threshold)
0x01 1 microframe
0x02 2 microframes
0x04 4 microframes
0x08 8 microframes
0x10 16 microframes
0x20 32 microframes
0x40 40 microframes
See bits 3–2 below. This is a non-EHCI bit.
endpoint. This bit is set and cleared by software. This bit shall also be cleared by hardware when is state
machine is hazard region where adding a dTD to a primed endpoint may go unrecognized. More information
on the use of this bit is described in
Setup tripwire. This is a non-EHCI bit. Used as a semaphore when the 8 bytes of setup data read extracted
from a QH by the DCD. If the setup lockout mode is off (See USBMODE) then there exists a hazard when
new setup data arrives and the DCD is copying setup from the QH for a previous setup packet. This bit is
set and cleared by software and will be cleared by hardware when a hazard exists. More information on the
use of this bit is described in
Reserved, should be cleared.
Asynchronous schedule park mode enable. Software uses this bit to enable or disable park mode. The reset
value of this field is always 1 after the USBDR controller is configured as a host by writing 0x3 to
USBMODE; else, the reset value is always 0.
0 Disabled
1 Enabled
Reserved, should be cleared.
13
0
0
Table 16-10. USBCMD Register Field Descriptions
12
—
0
0
Figure 16-8. USB Command Register (USBCMD)
—
ASPE
11
0
0
—
10
0
0
Section 16.9.2, “Device Operation.”
0
0
9
Section 16.9.2, “Device Operation.”
ASP
24
0
0
8
Description
LR
23
0
0
7
IAA
0
0
6
ASE
0
0
5
PSE
0
0
4
ITC
FS1
1
0
3
Freescale Semiconductor
FS0
0
0
2
Access: Mixed
RST
0
0
1
RS
16
0
0
0