MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 199

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

4.5.1.1
The reset configuration word low register (RCWLR) is shown in
Section 4.3.2.1, “Reset Configuration Word Low Register (RCWLR).”
4.5.1.2
The reset configuration word high register (RCWHR) is shown in
Section 4.3.2.2, “Reset Configuration Word High Register (RCWHR).”
4.5.1.3
RSR, shown in
For example, because software watchdog expiration results in a hard reset, SWRS and HRS are all set after
a software watchdog reset. This register returns to its reset value only when power-on reset occurs.
Table 4-28
Freescale Semiconductor
1
Address 0x0_0910
4–14
Bits
0x0_0924–
0–3
0x0_091C
0x0_09FC
The reset value of this field is determined according to the reset configuration input signals CFG_RESET_SOURCE[0:3]
sampled during the reset flow.
0x0_0920
Address
Reset
Reset
W
W
R
R
16 17
0
RSTSRC
Name
defines the reset status register bit fields.
—
—
RSTSRC
Reset Configuration Word Low Register (RCWLR)
Reset Configuration Word High Register (RCWHR)
Reset Status Register (RSR)
Table 4-27. Reset Configuration and Status Registers Memory Map (continued)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reset control register (RCR)
Reset control enable register (RCER)
Reserved, should be cleared.
18
Figure
n1
SWHR
Reset configuration word source. Reflects the value of CFG_RESET_SOURCE input signal during the
reset flow. See
has no effect.
Reserved, should be cleared.
19
3
4-8, captures various reset events in the device.The RSR accumulates reset events.
Table 4-28. Reset Status Register Field Descriptions
20
0
4
Section 4.3.1.1, “Reset Configuration Word Source,” on page
Register
Figure 4-8. Reset Status Register (RSR)
—
0
22
0
JSRS
23
0
All zeros
24
0
Description
—
Access
—
0
R/W
R/W
—
Figure 4-3
Figure 4-4
26
0
0x0000_0000
0x0000_0000
CSHR SWRS BMRS
and described in
27
and described in
Reset
0
Reset, Clocking, and Initialization
—
4-10. Changing this field
28
0
Access: User read/write
29
0
Section/Page
4.5.1.6/4-36
4.5.1.7/4-37
—
30
14
—
0
HRS
BSF
31
4-33
15
0