MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 379

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 8-19
8.5.12
SECNR, shown in
determines whether the corresponding IRQn signal asserts an interrupt request upon either a high-to-low
change or assertion on the pin. It also defines the IPIC output interrupt type (int, cint, or smi) in the
MIXA0–MIXA1 and MIXB0–MIXB1 priority positions.
Note that in core disabled mode of operation the user should use the int output interrupt type (should not
use cint or smi output interrupt types) in order to read an updated SIVCR.
Freescale Semiconductor
Offset 0x3C
Reset
Reset
17–31
5–15
Bits
0–4
16
W
W
R
R
EDI0
SIRQ0 Steer IRQ0.
Name
16
0
MIXB0T
—
—
—
defines the bit fields of SEMSR.
System External Interrupt Control Register (SECNR)
EDI1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
17
Each bit corresponds to an external interrupt source. The user masks an interrupt by clearing the SEMSR bit.
An interrupt can be enabled by setting the corresponding SEMSR bit.
SEMSR can be read by the user at any time.
Note:
Write ignored, read = 0
0 IRQ0 is used as external interrupt request
1 IRQ0 is used as external MCP request
Write ignored, read = 0
1
• SEMSR bit positions are not affected by their relative priority.
• The user can clear pending register bits that were set by multiple interrupt events only by clearing all
• If an SEMSR bit is masked at the same time that the corresponding SEPNR bit causes an interrupt request
unmasked events in the corresponding event register.
to the core, the error vector is issued (if no other interrupts pending). Thus, the user must always include an
error vector routine, even if it contains only an rfi instruction. The error vector cannot be masked.
Figure
EDI2
18
Figure 8-15. System External Interrupt Control Register (SECNR)
2
MIXB1T
EDI3
8-15, defines the edge detect mode for external IRQn interrupt signals and
19
3
EDI4
20
4
Table 8-19. SEMSR Field Descriptions
EDI5
21
—
EDI6
22
EDI7
23
7
All zeros
All zeros
Description
24
8
MIXA0T
9
Integrated Programmable Interrupt Controller (IPIC)
10
MIXA1T
11
—
12
Access: Read/write
—
15
31
8-21