MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 434

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
The value of the above parameters (in whole clock cycles) must be set by boot code at system start-up (in
the TIMING_CFG_0, TIMING_CFG_1, TIMING_CFG_2, and TIMING_CFG_3 registers as described
in
SDRAM Timing Configuration 1 (TIMING_CFG_1),” Section 9.4.1.6, “DDR SDRAM Timing
Configuration 2 (TIMING_CFG_2),”
(TIMING_CFG_3)”) and be kept in the DDR memory controller configuration register space.
The following figures show SDRAM timing for various types of accesses. System software is responsible
(at reset) for optimally configuring SDRAM timing parameters. The programmable timing parameters
apply to both read and write timing configuration. The configuration process must be completed and the
DDR SDRAM initialized before any accesses to SDRAM are attempted.
Figure 9-23
for a single-beat read operation,
burst-write operation. Note that all signal transitions occur on the rising edge of the memory bus clock and
that single-beat read operations are identical to burst-reads. These figures assume the CLK_ADJUST is
set to 1/2 DRAM cycle, an additive latency of 0 DRAM cycles is used, and the write latency is 1 DRAM
cycle (for DDR1).
9-40
Timing Intervals
Section 9.4.1.4, “DDR SDRAM Timing Configuration 0 (TIMING_CFG_0),” Section 9.4.1.5, “DDR
WRTORD
WRREC
SDRAM Clock
through
Figure 9-23. DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
MDQS
MRAS
MCAS
MDQ n
MWE
The number of clock cycles from the last beat of a write until a precharge command is allowed. This
interval, write recovery time, is listed in the AC specifications of the SDRAM as t
Last write pair to read command. Controls the number of clock cycles from the last write data pair to the
subsequent read command to the same bank as t
MCS
MA n
Figure 9-25
Table 9-31. DDR SDRAM Interface Timing Intervals (continued)
ROW
0
Figure 9-24
1
show DDR SDRAM timing for various types of accesses; see
ACTTORW
2
and
COL
Section 9.4.1.3, “DDR SDRAM Timing Configuration 3
3
for a single-beat write operation, and
CASLAT
4
COL
5
D0
Definition
D1 D2 D3
6
WTR
.
7
D0
D1 D2
8
D3
9
10
Figure 9-25
Freescale Semiconductor
11
WR
.
12
Figure 9-23
for a