MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1125

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

18.3.1.13 DMA Status Registers (UDSR1 and UDSR2)
The DMA status registers (UDSRs), shown in
and provide the ability to assist DMA data operations to and from the FIFOs.
Table 18-20
Freescale Semiconductor
DMS
DMS
Bits
0–5
6
7
0
0
1
1
0
0
1
1
RXRDY Receiver ready. This read-only bit reflects the status of the receiver FIFO or URBR. The status depends on
TXRDY
Name
FEN
FEN
Offset: 0x0_4510, 0x0_4610
Reset
0
1
0
1
0
1
0
1
—
describes the fields of the UDSRs.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
W
R
DMA Mode
DMA Mode
Reserved
Transmitter ready. Reflects the status of the transmitter FIFO or the UTHR. The status depends on the DMA
mode selected, which is determined by UFCR[DMS] and UFCR [FEN].
0 The bit is cleared, as shown
1 This bit is set, as shown in
the DMA mode selected, which is determined by UFCR[DMS] and UFCR [FEN].
0 The bit is cleared, as shown in
1 This bit is set, as shown in
0
0
0
0
0
1
0
0
0
1
TXRDY is set after the first character is loaded into the transmitter FIFO or UTHR.
TXRDY is set when the transmitter FIFO is full.
TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR.
TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR. TXRDY
remains clear while the transmitter FIFO is not yet full.
Table 18-22. UDSR[TXRDY] Cleared Conditions
0
Figure 18-15. DMA Status Register (UDSR)
Table 18-21. UDSR[TXRDY] Set Conditions
Table 18-20. UDSR Field Descriptions
0
Table
Table
inTable
Table
—
Figure
18-21.
18-23.
18-22.
18-24.
0
18-15, return transmitter and receiver FIFO status
Description
0
Meaning
Meaning
0
5
Access: User read-only
TXRDY
0
6
RXRDY
1
7
DUART
18-17