MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 201

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

4.5.1.4
RMR, shown in
checkstop state.
Table 4-29
4.5.1.5
RPR, shown in
control register (RCR). To disable a write to the reset control register (RCR), the user should write a 1 to
RCER[CRE].
Freescale Semiconductor
Address 0x0_0914
Address 0x0_0918
0–30
Bits
31
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
CSRE Checkstop reset enable. The core can enter checkstop mode as the result of several exception conditions.
Name
—
16
16
0
0
describes the RMR fields.
Reset Mode Register (RMR)
Reset Protection Register (RPR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, should be cleared.
Setting CSRE configures the device to perform a hard reset sequence when the core enters checkstop state.
0 Reset not generated when core enters checkstop state.
1 Reset generated when core enters checkstop state.
Figure
Figure
4-10, prevents unintended software reset requests caused by writes to the reset
4-9, enables a hard reset sequence on the device when the e300 core enters
Figure 4-10. Reset Protection Register (RPR)
Figure 4-9. Reset Mode Register (RMR)
Table 4-29. RMR Field Descriptions
—
All zeros
All zeros
All zeros
All zeros
RCPW
RCPW
Function
—
Reset, Clocking, and Initialization
Access: User read/write
Access: User read/write
30
CSRE
15
31
15
31
4-35