MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1067

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

when the associated bit in the ENDPTPRIME register is zero and the associated bit in the ENDPTSTATUS
register is a one. If a prime fails, that is, The ENDPTPRIME bit goes to zero and the ENDPTSTATUS bit
is not set, then the prime has failed. This can only be due to improper setup of the dQH, dTD or a setup
arriving during the prime operation. If a new setup packet is indicated after the ENDPTPRIME bit is
cleared, then the transfer descriptor can be freed and the DCD must reinterpret the setup packet.
Should a setup arrive after the data stage is primed, the device controller will automatically clear the prime
status (ENDPTSTATUS) to enforce data coherency with the setup packet.
16.8.3.5.3
Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and prime
the endpoint for the status phase. The DCD must also perform the same checks of the ENDPTSETUPSTAT
as described above in the data phase.
16.8.3.5.4
Shown in the following table is the device controller response to packets on a control endpoint according
to the device controller state.
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
The MULT field in the dQH must be set to ‘00’ for bulk, interrupt, and
control endpoints.
Error handling of data phase packets is the same as bulk packets described
previously.
Status Phase
The MULT field in the dQH must be set to ‘00’ for bulk, interrupt, and
control endpoints.
Error handling of data phase packets is the same as bulk packets described
previously.
Control Endpoint Bus Response Matrix
Token
Setup
Type
Out
In
STALL
STALL
Table 16-89. Control Endpoint Bus Response Matrix
Stall
ACK
Primed
ACK
NAK
NAK
Not
Endpoint State
NYET/ACK
Receive +
Transmit
Primed
NOTE
NOTE
NOTE
NOTE
ACK
3
Underflow
BS Error
N/A
N/A
2
SYSERR
Overflow
NAK
N/A
1
Universal Serial Bus Interface
Lockout
Setup
N/A
N/A
16-139