MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 919

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 15-173
Freescale Semiconductor
Set up the MII Mgmt for a write cycle to the external PHY Control register (write the PHY address and Register address),
This enables the external PHY to restart Auto-Negotiations using the configuration set in the AN Advertisement register.
Set up the MII Mgmt for a write cycle to external the PHY AN Advertisement register (write the PHY address
The AN Advertisement register is at offset address 0x04 from the external PHY address. (in this case 0x11)
Write to MII Mgmt Control with 16-bit data intended for the external PHY AN Advertisement register,
The control register is at offset address 0x00 from the external PHY address. (in this case 0x11)
describes the register initializations required to configure the eTSEC in RMII mode.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Write to MII Mgmt Control with 16-bit data intended for the external PHY Control register,
set system clock divide by 14 for example to insure that MDC clock speed = 2.5 MHz
(Used to setup Reduced-Pin mode = 1, and TBIM = 0,statistics enable = 1)
Where u must be selected by the user for proper system configuration.
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
Table 15-173. RMII Mode Register Initialization Steps
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
MIIMCON[0000_0000_0000_0000_u0uu_uuuu_uuuu_uuuu]
MIIMCON[0000_0000_0000_0000_0001_0010_0000_0000]
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_1101]
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0100]
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0000]
ECNTRL[0000_0000_0000_0000_0001_0000_0001_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt write cycle to the external PHY.
This indicates that the eTSEC MII Mgmt bus is idle.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete.
Setup the MII Mgmt clock speed,
to 02608C:876543 for example
to 02608C:876543 for example
(I/F Mode = 2, Full Duplex = 1)
Initialize MAC Station Address
Initialize MAC Station Address
and Register address),
Initialize MACCFG2,
Initialize ECNTRL,
Clear Soft_Reset,
Set Soft_Reset,
Enhanced Three-Speed Ethernet Controllers
15-201