MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 949

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Note that this register is shared between the host and device mode functions. In host mode, it is the
ASYNCLISTADDR register; in device mode, it is the ENDPOINTLISTADDR register. See
Section 16.3.2.9, “Endpoint List Address Register (ENDPOINTLISTADDR)—Non-EHCI,”
information.
16.3.2.9
This register is not defined in the EHCI specification. In device mode, this register contains the address of
the top of the endpoint list in system memory. Bits 10–0 of this register cannot be modified by the system
software and always return zeros when read. The memory structure referenced by this physical memory
pointer is assumed to be 64-bytes. The queue head is actually a 48-byte structure, but must be aligned on
64-byte boundary. However, the ENDPOINTLISTADDR[EPBASE] has a granularity of 2 Kbytes, so in
practice the queue head should be 2-Kbyte aligned.
Note that this register is shared between the host and device mode functions. In device mode, it is the
ENDPOINTLISTADDR register; in host mode, it is the ASYNCLISTADDR register. See
Section 16.3.2.8, “Current Asynchronous List Address Register (ASYNCLISTADDR),”
information.
Freescale Semiconductor
Offset 0x2_3158
Reset
31–5
Offset 0x2_3158
Reset
Bits
4–0
W
R
W
R
31
31
ASYBASE
Name
—
Endpoint List Address Register (ENDPOINTLISTADDR)—Non-EHCI
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 16-14. Current Asynchronous List Address (ASYNCLISTADDR)
Link pointer low (LPL). These bits correspond to memory address signals [31:5]. This field may only
reference a queue head (QH). Only used by the host controller.
Reserved, should be cleared.
Figure 16-15. Endpoint List Address (ENDPOINTLISTADDR)
Table 16-17. ASYNCLISTADDR Register Field Descriptions
EPBASE
ASYBASE
All zeros
All zeros
Description
11 10
Universal Serial Bus Interface
Access: Read/Write
5
—
Access: Read/Write
for more
4
for more
—
16-21
0
0