MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 997

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.6.2
The HCSPARAMS[PPC] bit indicates whether the USB 2.0 host controller has port power control. When
the PPC bit is set, the host controller supports port power switches. Each available switch has an output
enable. PPE is controlled based on the state of the combination bits PPC bit, EHCI Configured (CF)-bit
and individual Port Power (PP) bits.
16.6.3
Host ports by definition are power providers on USB. Whether the ports are considered high- or
low-powered is a platform implementation issue. The EHCI PORTSC register has an over-current status
and over-current change bit. The functionality of these bits is specified in the USB Specification Revision
2.0.
The over current detection and limiting logic resides outside the DR logic. The over-current condition
effects the following bits in the PORTSC register on the EHCI port:
16.6.4
The host controller provides an equivalent suspend and resume model as that defined for individual ports
in a USB 2.0 hub. Control mechanisms are provided to allow system software to suspend and resume
individual ports. The mechanisms allow the individual ports to be resumed completely through software
initiation. Other control mechanisms are provided to parameterize the host controller's response (or
sensitivity) to external resume events. In this discussion, host-initiated, or software-initiated resumes are
called Resume Events/Actions; bus-initiated resume events are called wake-up events. The classes of
wakeup events are:
Freescale Semiconductor
•
•
•
•
•
•
Over-current active bit (OCA) is set. When the over-current condition goes away, the OCA will
transition from a one to a zero.
Over-current change bit (OCC) is set. On every transition of OCA, the controller will set OCC to
a one. Software sets OCC to a zero by writing a one to this bit.
Port enabled/disabled bit (PE) is cleared. When this change bit gets set, USBSTS[PCI] (the port
change detect bit) is set.
Port power (PP) bit may optionally be cleared. There is no requirement in USB that a power
provider shut off power in an over current condition. It is sufficient to limit the current and leave
power applied. When OCC transitions from a zero to a one, the controller also sets USBSTS[PCI]
to a one. In addition, if the Port Change Interrupt Enable bit, USBINTR[PCE], is a one, the
controller issues an interrupt to the system. Refer to
over-current detection when the controller is halted (suspended from a device component point of
view).
Remote-wakeup enabled device asserts resume signaling. In similar kind to USB 2.0 hubs, when
in host mode the host controller responds to explicit device resume signaling and wake up the
system (if necessary).
Port connect and disconnect and over-current events. Sensitivity to these events can be turned on
or off by using the port control bits in the PORTSC register.
Power Port
Reporting Over-Current
Suspend/Resume
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 16-64
for summary of behavior for
Universal Serial Bus Interface
16-69