MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 524

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
For proper signalling, the following guidelines must be followed while programming UPM RAM words:
10.4.4.2.1
The following example further illustrates the steps required to perform two writes to the RAM array at
non-sequential addresses assuming that the relevant BR
Note that if step 1 (or 6) and 2 (or 7) are reversed, step 3 (or 8) is replaced by the following:
10-76
•
•
•
•
1. Program M
2. Write pattern/data to MDR to ensure that the MxMR has already been updated with the desired
3. Read MDR to ensure that the MDR has already been updated with the desired pattern. (Or, read
4. Perform a dummy write transaction.
5. Read/check M
6. Program M
7. Write pattern/data to MDR to ensure that the M
8. Read MDR to ensure that the MDR has already been updated with the desired pattern.
9. Perform a dummy write transaction.
10. Read/check M
•
For UPM reads, program UTA and LAST in the same or consecutive RAM words.
For UPM burst reads, program last UTA and LAST in the same or consecutive RAM words.
For UPM writes, program UTA and LAST in the same RAM word.
For UPM burst writes, program last UTA and LAST in the same RAM word.
configuration.
MxMR register if step 2 is not performed.)
proceed to step 6. Repeat step 5 until incremented.
configuration.
Read M
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
In order to enforce proper ordering between updates to the MxMR/MDR
register and the dummy accesses to the UPM memory region, two rules
must be followed:
1. Since the result of any update to the MxMR/MDR register must be in effect before the
2. The UPM memory region should have the same MMU settings as the memory region
UPM Programming Example (Two Sequential Writes to the RAM Array)
x
MR to ensure that the M
dummy read or write to the UPM region, a write to MxMR/MDR should be followed
immediately by a read of MxMR/MDR.
containing the MxMR configuration register; both should be mapped by the MMU as
cache-inhibited and guarded. This prevents the CPU from re-ordering a read of the
UPM memory around the read of MxMR. Once the programming of the UPM array is
complete the MMU setting for the associated address range can be set to the proper
mode for normal operation, such as cacheable and copyback.
x
x
MR for the first write (with the desired RAM array address).
MR for the second write with the desired RAM array address.
x
x
MR[MAD]. If incremented, the previous dummy write transaction is completed;
MR[MAD]. If incremented, the previous dummy write transaction is completed.
x
MR has already been updated with the desired configuration.
x
n
MR has already been updated with the desired
and OR
n
registers have been previously set up:
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