MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1208

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

P–P
PCI_C/BE[7:0] (PCI command/byte enable) signals, 13-6
PCI_CLK, 4-4
PCI_CLK_OUT[0:7], 4-4, 4-30
PCI_PERR (PCI parity error) signal, 13-9
PCI_PME (PCI PME) signal, 13-9
PCI_REQ[4:0] (PCI bus request) signals, 13-9
PCI_SERR (PCI system error) signal, 13-10
PCI_STOP (PCI stop) signal, 13-10
PCI_SYNC_IN, 4-4
PCI_SYNC_OUT, 4-4
PCI_TRDY (PCI target ready) signal, 13-11
Index-10
registers, 13-12–13-40
signals, 13-4–13-11
read and write transactions, 13-49
transaction termination, 13-51
configuration access, 13-12–13-15
configuration space, 13-25–13-40
control and status, 13-15–13-25
burst read example, 13-50
burst write example, 13-51
single beat read example, 13-49
single beat write example, 13-50
target-initiated terminations, 13-52
base class code, 13-31
BIST control, 13-33
cache line size, 13-32
capabilities pointer, 13-36
device ID, 13-27
GPL base address register 0, 13-34
GPL base address registers 1,2, 13-34
GPL extended base address registers 1,2, 13-35
header type, 13-33
hot swap register block, 13-40
interrupt line, 13-37
interrupt pin, 13-37
latency timer, 13-32
MAX LAT, 13-38
MIN GNT, 13-37
PCI arbiter control, 13-39
PCI command, 13-28
PCI function, 13-38
PCI power management register 0 (PCIPMR0), 13-41
PCI power management register 1 (PCIPMR1), 13-42
PCI status, 13-29
PIMMR base address, 13-33
revision ID, 13-30
standard programming interface, 13-30
subclass code, 13-31
sub-system device ID, 13-36
sub-system vendor ID, 13-36
vendor ID, 13-27
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
Performance
Performance monitor, 7-12
Performance monitor APU
Periodic interval timer (PIT), 5-42
PHY clocks, 16-5
PHY interface, 16-46
PIC, see IPIC
PKEU
Power management
Power management control, 5-64
Power saving mode
Power-on reset (POR)
PowerPC architecture
Privilege level (PR), 7-17
Processor core, see e300 processor core
Program interrupt, 7-33
Programmable interrupt controller, see IPIC
characterizing through performance monitor event
interrupt triggered by events, 7-12
block diagram, 5-43
external signal description, 5-43
features, 5-43
functional block diagram, 5-47
functional description, 5-47
memory map/register definition, 5-44
modes of operation, 5-43
operational modes, 5-48
overview, 5-42
registers, 5-44–5-47
EU_GO register, 14-27, 14-38
status register, 14-23
DDR interface, 9-45
modes, 7-11
external signal description, 5-65
functional description, 5-72
initialization/application information, 5-91
memory map/register definition, 5-65
registers, 5-66–5-69
SEC, 14-75
flow, 4-6
output signal states during reset, 3-13
reset configuration signals, 3-12
timing diagram, 4-8
levels of implementation, 7-13
overview, 7-13
dynamic power management, 5-72
exiting low power states, 5-78
shutting down unused blocks, 5-73
software-controlled power-down states, 5-73
counting, 7-12
Freescale Semiconductor
Index