MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 700

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
14-58
Bits
38
39
40
41
42
43
44
45
Names
PRD
SRD
MO
PG
SG
PR
SR
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
MI
Multi_EU_IN. The Multi_EU_IN bit reflects the type of snooping the channel will perform, as
programmed by the “Snoop Type” bit in the descriptor header.
0 Data input snooping by secondary EU disabled.
1 Data input snooping by secondary EU enabled.
Multi_EU_OUT. The Multi_EU_OUT bit reflects the type of snooping the channel will perform, as
programmed by the “Snoop Type” bit in the descriptor header.
0 Data output snooping by secondary EU disabled.
1 Data output snooping by secondary EU enabled.
PRI_REQ. Request primary EU assignment.
0 Primary EU Assignment Request is inactive.
1 The channel is requesting assignment of primary EU to the channel. The channel will assert the
The PRI_REQ bit is set when descriptor processing is initiated by the channel and the Op_0 field in
the descriptor header contains a valid EU identifier. This bit is cleared when the request is granted,
which will be reflected in the status register by the setting the PRI_GRANT bit.
SEC_REQ. Request secondary EU assignment.
0 Secondary EU Assignment Request is inactive.
1 The channel is requesting assignment of secondary EU to the channel. The channel will assert
The SEC_REQ bit is set when descriptor processing is initiated by the channel and the Op_1 field
in the descriptor header contains a valid EU identifier. This bit is cleared when the request is granted,
which will be reflected in the status register by the setting the SEC_GRANT bit.
Primary EU granted. The PRI_GRANT bit reflects the state of the EU grant signal for the requested
primary EU from the controller.
0 The primary EU grant signal is inactive.
1 The EU grant signal is active indicating the controller has assigned the requested primary EU to
Secondary EU granted. The SEC_GRANT bit reflects the state of the EU grant signal for the
requested secondary EU from the controller.
0 The secondary EU grant signal is inactive.
1 The EU grant signal is active indicating the controller has assigned the requested secondary EU
Primary EU reset done. The PRI_RST_DONE bit reflects the state of the reset done signal from the
assigned primary EU.
0 The assigned primary EU reset done signal is inactive.
1 The assigned primary EU reset done signal is active indicating its reset sequence has completed
Secondary EU reset done. The SEC_RST_DONE bit reflects the state of the reset done signal from
the assigned secondary EU.
0 The assigned secondary EU reset done signal is inactive.
1 The assigned secondary EU reset done signal is active indicating its reset sequence has
EU request signal indicated by the op0 field in the Descriptor Header register as long as this bit
remains set.
the EU request signal indicated by the Op_1 field in the descriptor header register as long as this
bit remains set.
the channel.
to the channel.
and it is ready to accept data.
completed and it is ready to accept data.
Table 14-32. CCPSR Field Descriptions (continued)
Description
Freescale Semiconductor