MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 572

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DMA/Messaging Unit
12.3.8.3
DMACDARn contains the address of the current segment descriptor being transferred. In chaining mode,
software must initialize this register to point to the first descriptor in the chain. After processing the first
descriptor, the DMA controller moves the contents of the next descriptor address register into
DMACDAR, loads the following descriptor into DMANDAR, and executes the current transfer.
Figure 12-12
Table 12-12
12-12
Offset 0x108, 0x188, 0x208, 0x288
31–5
Reset
Bits
Bits
2–0
1
0
4
3
W
R
31
EOCDI
EOSIE
Name
Name
SNEN
EOSI
CDA
—
describes the DMACDARn register.
DMA Current Descriptor Address Register (DMACDAR n )
shows the DMACDARn fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
End-of-segment interrupt. After transferring a segment of data, if the DMACDAR n[ EOSIE] bit in the current
descriptor address register is set, this bit is set and an interrupt is generated.
End-of-chain/direct interrupt. When the last DMA transfer is finished, either in chaining or direct mode, if
DMAMR[EOTIE] is set, this bit is set and an interrupt is generated.
Current descriptor address. This field contains the current descriptor address of the segment descriptor in
memory. It must be aligned on an 8-word boundary.
Snoop enable.
0 Snooping is disabled on DMA transactions of the current segment.
1 Snooping is enabled on DMA transactions of the current segment.
End-of-segment interrupt enable
0 No end-of-segment interrupt is generated.
1 An interrupt is generated when the current DMA transfer for the current descriptor is finished.
Reserved
Figure 12-12. DMA Current Descriptor Address Register (DMACDAR n )
Table 12-11. DMASR n Field Descriptions (continued)
Table 12-12. DMACDAR n Field Descriptions
CDA
All zeros
Description
Description
5
Access: User Read/Write
SNEN EOSIE
Freescale Semiconductor
4
3
2
—
1
0