MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1168

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Revision History
10.4.2.3.2, 10-51
10.4.3.4.1, 10,70
10.4.3.4.2, 10-71
10.4.4.1.2, 10-74
A-10
1
TRLX
Times in parentheses are specific for the case LCRR[CLKDIV] = 2; other times apply to all CLKDIV
values.
Option Register Attributes
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
XACS
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
In the second paragraph, third sentence, changed to read: ‘ORn[CSNT], along
with ORn[TRLX], control ...’.
In Table 10-36, changed the setting for field SCY to read: From por_cfg_scy[1:3].
Changed step 4, first paragraph, to read:
4. If ECC checking is enabled, the FCM recovers from the spare region the stored
Second paragraph, replaced with the following:
ACS
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
ECC for each 512-byte block of boot data. The boot block must be prepared
with ECC protection. During ECC generation, software should use
FMR[ECCM] = 0 for small-page devices, and FMR[ECCM] = 1 for large-page
devices.
CSNT
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
t
AWCS
(1½)
(1½)
1¼
1½
1¼
1½
0
1
2
0
0
2
3
0
0
2
3
(½+2×SCY)
(½+2×SCY)
1¾+2×SCY
1½+2×SCY
1½+2×SCY
1¼+2×SCY
(2+2×SCY)
(1+2×SCY)
¾+2×SCY
¾+2×SCY
2+2×SCY
2+2×SCY
1+2×SCY
1+2×SCY
3+2×SCY
3+2×SCY
(½+SCY)
(½+SCY)
Signal Timing (LCLK Clock Cycles)
¾+SCY
¾+SCY
2+SCY
t
CSWP
t
AWE
1
1
2
1
2
2
1
2
3
1
2
2
1
2
3
t
WEN
1¼
1¼
(0)
(1)
(1)
¼
0
0
0
0
0
0
0
0
0
0
0
0
1
Freescale Semiconductor
(2½+2×SCY)
(2½+2×SCY)
(2½+2×SCY)
(3½+2×SCY)
2¾+2×SCY
2¾+2×SCY
2¾+2×SCY
3¾+2×SCY
(1½+SCY)
(2½+SCY)
2+2×SCY
3+2×SCY
3+2×SCY
2+2×SCY
3+2×SCY
4+2×SCY
3+2×SCY
3+2×SCY
1¾+SCY
2¾+SCY
2+SCY
t
WC