MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 337

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

7.3.1.3.2
For memory management, 32-bit processors implement sixteen 32-bit SRs. To speed access, the core
implements the SRs as two arrays: a main array, for data memory accesses, and a shadow array, for
instruction memory accesses. Loading a segment entry with the Move to Segment Register (mtsr)
instruction loads both arrays.
7.3.1.3.3
The e300 core, like the G2_LE core, has additional supervisor-level SPRs, which are shown in
Two critical interrupt SPRs (CSRR0 and CSRR1), eight SPRGs (SPRG0–SPRG7), eight pairs of
instruction BATs (IBAT0–IBAT7), eight pairs of data BATs (DBAT0–DBAT7), one system version
register (SVR), one system memory base address (MBAR), one instruction address breakpoint control
(IBCR), one data address breakpoint control (DBCR), a new instruction breakpoint register (IABR2), and
two data address breakpoint registers (DABR and DABR2) are integrated into the core.
Supervisor-level SPRs include the following:
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
The DSISR defines the cause of data access and alignment interrupts. The cause of a DSI interrupt
for a data breakpoint (match with DABR and DABR2) can be determined by the value of the
DSISR[DABR] bit (bit 9).
The data address register (DAR) holds the address of an access after an alignment or DSI interrupt.
For example, it contains the address of the breakpoint match condition.
The decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for
causing a decrementer interrupt after a programmable delay.
SDR1 specifies the page table format used in virtual-to-physical address translation for pages.
(Note that physical address is referred to as ‘real address’ in the architecture specification.)
The machine status save/restore register 0 (SRR0) is used for saving the address of the instruction
that caused the interrupt, and the address to return to when a Return from Interrupt (rfi) instruction
is executed.
The machine status save/restore register 1 (SRR1) is used to save machine status on interrupts and
to restore machine status when an rfi instruction is executed.
The SPRG0–SPRG7 registers are provided for operating system use. They reduce the latency that
may be incurred in the saving of registers to memory while in a handler. Note that the e300
implements four more SPRGs than the G2 (SPRG0–SPRG3).
The time base register (TB) is a 64-bit register that maintains the time of day and operates interval
timers. It consists of two 32-bit fields: time base upper (TBU) and time base lower (TBL).
The processor version register (PVR) is a read-only register that identifies the version (model) and
revision level of the processor. See
e300 processor core.
Block address translation (BAT) arrays—The PowerPC architecture defines 16 BAT registers. The
e300 core includes a total of eight pairs of DBAT and eight pairs of IBAT registers. See
for a list of the SPR numbers for the BAT arrays.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Segment Registers (SRs)
Supervisor-Level SPRs
Table 7-8
for the version and revision level of the PVR for the
e300 Processor Core Overview
Figure
Figure 7-2
7-3.
7-19