MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1178

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Revision History
15.7.1.6, 15-203
15.7.1.6, 15-204
16.3, 16-5
16.3, 16-5
16.3, 16-5
16.3.1.3, 16-9
16.3.2.12, 16-23
16.3.2.12 ULPI Register Access (ULPI VIEWPORT)
The register provides indirect access to the ULPI PHY register set. Although the controller modules
perform access to the ULPI PHY register set, there may be extraordinary circumstances where software
may need direct access. Be advised that writes to the ULPI through the ULPI viewport can substantially
harm standard USB operations. Currently no usage model has been defined where software should need
to execute writes directly to the ULPI. Note that executing read operations though the ULPI viewport
should have no harmful side effects to standard USB operations. Also note that if the ULPI interface is not
enabled, this register will always read zeros.
A-20
This advertises to the Link Partner that the TBI supports PAUSE and Full Duplex mode and does not support Half Duplex mode.
0x2_3170
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Writing to MII Mgmt Control with 16-bit data intended for TBI’s AN Advertisement register,
ULPI VIEWPORT—ULPI Register Access
Replaced the first paragraph with the following:15.7.1.6, 15-203In Table 15-179,
removed references to TBICON[Enable Wrap] and TBICON[Comma Detect].
In Table 15-179, changed the following row to read:
In Table 16-3, Section/Page column, corrected page numbers.
In Table 16-3, added the following row:
In Table 16-3, changed the reset value for the following addresses:
In Table 16-6, “HCSPARAMS Register Field Descriptions,” removed "The reset
value of this field is always 0 after the USBDR controller is configured as a host
by writing 0x3 to USBMODE; else, the reset value is always 1” from
HCSPARAMS[N_PCC] bit field description.
Added the following new section, figure, and table. Renumbered the following
sections, figures, and tables.
MIIMCON[0000_0000_0000_0000_0000_0001_1010_0000]
Address Offset
0x2_3104
0x2_3124
0x2_3140
0x2_3164
0x2_3184
0x2_31A4
Perform an MII Mgmt write cycle to TBI.
Value
0x0001_0011
0x0000_0183
0x0008_0000
0x0000_0000
0x1000_0000
0x0000_0C20
Mixed
0x0000_0000
Freescale Semiconductor
16.3.2.12/16-24