MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 312

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Arbiter and Bus Monitor
6.2.8
Arbiter event response register (AERR) determines whether different error conditions cause interrupt or
reset request. Setting a bit defines the corresponding error condition to cause reset request; clearing a bit
defines the corresponding error condition to cause interrupt.
Table 6-9
6.3
The following sections describe arbiter functionality: arbitration policy and bus error detection.
6.3.1
The arbitration process involves the masters and the arbiter. Masters arbitrate on the privilege to own an
address tenure. For data tenures, the arbiter uses the same order of transactions as address tenures.
6-10
Offset 0x20
Reset
0–25
Bits
26
27
28
29
30
31
W
R
0
Functional Description
describes AERR field.
Name
ETEA
ECW
RES
DTO
ATO
AO
—
Arbiter Event Response Register (AERR)
Arbitration Policy
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Write reserved, read = 0
Transfer error. Detection of transfer error by one of the slaves event response.
0 Detection of transfer error by one of the slaves causes interrupt.
1 Detection of transfer error by one of the slaves causes reset request.
Reserved transfer type. Transaction with reserved transfer type interrupt definition.
0 Transaction with reserved transfer type causes interrupt.
1 Transaction with reserved transfer type causes reset request.
External control word transfer type. Transaction with external control word transfer type interrupt
definition.
0 Transaction with external control word transfer type causes interrupt.
1 Transaction with external control word transfer type causes reset request.
Address only transfer type. Transaction with address only transfer type interrupt definition.
0 Transaction with address only transfer type causes interrupt.
1 Transaction with address only transfer type causes reset request.
Data time out. Data tenure time out interrupt definition.
0 Data tenure time out causes interrupt.
1 Data tenure time out causes reset request.
0 Address tenure time out causes interrupt.
1 Address tenure time out causes reset request.
Address time out. Address tenure time out interrupt definition.
Figure 6-8. Arbiter Event Response Register (AERR)
Table 6-9. AERR Field Descriptions
—
All zeros
Description
Figure 6-8
shows the fields of AERR.
25
ETEA RES ECW AO DTO ATO
26
27
Freescale Semiconductor
Access: User read/write
28
29
30
31