MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 942

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.3.2.2
This register indicates various states of the USB DR module and any pending interrupts. This register does
not indicate status resulting from a transaction on the serial bus. Software clears certain bits in this register
by writing a 1 to them (indicated by a w1c in the bit’s W cell in
16-14
Offset 0x2_3144
Reset
Reset
Bits
1
0
W
W
R
R
AS
31
15
Name
RST
RS
USB Status Register (USBSTS)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PS
14
Controller reset. Software uses this bit to reset the controller. This bit is cleared by the controller when the
reset process is complete. Software cannot terminate the reset process early by writing a zero to this
register.
Host mode:
Device mode:
Run/Stop.
Host mode:
Device mode:
0 Stop
1 Run
• When software sets this bit, the host controller resets its internal pipelines, timers, counters, state
• When software sets this bit, the USB DR controller resets its internal pipelines, timers, counters, state
• When this bit is set, the controller proceeds with the execution of the schedule. The controller continues
• Setting this bit will cause the USB DR controller to enable a pull-up on D+ and initiate an attach event.
machines etc. to their initial value. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. Software should not set this bit when
USBSTS[HCH] is a zero. Attempting to reset an actively running host controller will result in undefined
behavior.
machines etc. to their initial value. Any transaction currently in progress on USB is immediately
terminated. Writing a one to this bit in device mode is not recommended.
execution as long as this bit is set. When this bit is set to 0, the host controller completes the current
transaction on the USB and then halts. The USBSTS[HCH] bit indicates when the USB DR controller has
finished the transaction and has entered the stopped state. Software should not write a one to this field
unless the controller is in the halted state (that is, USBSTS[HCH] is a one).
This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon
transitioning into high-speed mode. Software should use this bit to prevent an attach event before the
controller has been properly initialized. Clearing this bit will cause a detach event.
RCL
Table 16-10. USBCMD Register Field Descriptions (continued)
13
HCH
12
Figure 16-9. USB Status Register (USBSTS)
—
11
ULPII
10
—
9
w1c
SLI
All zeros
All zeros
8
—
Description
w1c
SRI
7
URI
w1c
Figure
6
w1c
AAI
5
16-9).
w1c
SEI
4
w1c
FRI
3
Freescale Semiconductor
w1c
PCI
2
Access: Mixed
w1c
UEI
1
w1c
UI
16
0