MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 703

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 14-35
1
Table 14-36
Freescale Semiconductor
Value
Invalid opcode includes any opcode valid on other versions of the SEC but not valid on SEC 2.2.
48
49
50
51
52
53
54
55
56
57
58
59
DOF. Double fetch FIFO write overflow error. This bit is set when the channel Fetch FIFO is full, SOF is set, and
another write has been made to the fetch FIFO. When this bit is set the channel will stop, and an error interrupt will
be activated. The channel will not start again until a Continue or Reset is given through the CCR register. This bit
can be cleared by writing ‘1’ to this bit in the CPSR register.
SOF. Single fetch FIFO write overflow error. This bit is set when the channel Fetch FIFO is full and another write has
been made to the Fetch FIFO. The channel will set this bit and activate an error interrupt. The channel continues
processing, but the descriptor pointer is lost. The host must clear this bit by writing ‘1’ to this bit in the CPSR register.
MDTE. A Master data transfer error was received from the master bus interface. When the SEC, while acting as a
bus master, detects an error, the controller passes the error to the channel in use. The channel halts and activates
an interrupt. The channel can only be restarted by writing a ‘1’ to the Continue or Reset bit in the channel
configuration register, or resetting the whole SEC.
Scatter/Gather data length zero error. A zero length Scatter/Gather data pointer was detected.
Fetch pointer zero error. An all zero fetch pointer was detected.
Illegal descriptor header. Possible causes of an illegal descriptor header are:
Invalid EU assignment request. Indicates the channel has been assigned one or more EUs not requested by the
descriptor header.
EU error detected. An EU assigned to this channel has generated an error interrupt. This error may also be reflected
in the controller's interrupt status register.
Gather boundary error. Indicates a gather pointer straddles both a primary and secondary EU’s data transfer.
Gather return/length error. Indicates the total data size covered by a gather link table did not match the total data size
from the main descriptor.
Scatter boundary error. Indicates a scatter pointer straddles both a primary and secondary EU’s data transfer.
Scatter return/length error. Indicates the total data size covered by a scatter link table did not match the total data
size from the main descriptor.
• Invalid primary EU indicated by op0 field in descriptor header.
• Invalid secondary EU indicated by op1 field in descriptor header.
• Descriptor type field in descriptor header indicates secondary EU transaction when not in snoop mode
shows the bit positions of each potential error. Multiple errors are possible.
shows the possible values of the PAIR_PTR field in the CCPSR.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
EU error bit (bit 55) can only be cleared by first clearing the error source in
the assigned EU which caused it to be set.
Table 14-36. Crypto-Channel Pointer Status Register PAIR_PTR Field Values
Table 14-35. Crypto-Channel Pointer Status Register Error Field Definitions
Value
0x00
0x01
0x02
Processing header or pointer dword 0
Processing pointer dword 1
Processing pointer dword 2
NOTE
Error
Error
1
Security Engine (SEC) 2.2
14-61