MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 755

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.5.3.2.2
This register is read/write-one-to-clear and is written by the eTSEC to convey DMA status information for
each TxBD ring. The halt bit only has meaning for enabled rings. After processing transmit-related
interrupts, software should use TSTAT to restart transmission from rings that may have been affected by
the interrupt condition. In particular, an error condition that prevents eTSEC from continuing transmission
halts DMA from all rings, including the ring that gave rise to the error.
register.
Freescale Semiconductor
Offset eTSEC1:0x2_4104; eTSEC2:0x2_5104
Reset
Reset
29–30
Bits
31
W
W
R THLT0
R
TXF0
w1c
w1c
TXSCHED Transmit ring scheduling algorithm. This field determines which scheme the transmit scheduler uses to
16
0
Name
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Transmit Status Register (TSTAT)
THLT1
TXF1
w1c
w1c
17
1
arbitrate between the enabled TxBD rings. The scheme chosen also controls how the DMACTRL and
TQUEUE bits are interpreted. Ring polling is supported only by mode 00; the other modes require
software to restart rings with the TSTAT register. TCP/IP offload can be enabled with any scheduling
mode.
00 Single polled ring mode. TxBD ring 0 is the only ring serviced, even if other rings are enabled and
01 Priority scheduling mode. All enabled TxBD rings are serviced in ascending ring index order. Once
10 Modified weighted round-robin scheduling mode. Each TxBD ring is polled in sequence for frames
11 Reserved
Reserved
ready. In this scheduler mode, the DMACTRL[WOP] and DMACTRL[TOD] bits control polling and
retry behavior. This mode supports ring polling, and allows fetching of a non-ready TxBD to be retried
twice.
a non-ready TxBD has been fetched from the lowest-numbered ring, the eTSEC attempts to fetch
TxBDs from the next enabled ring having a higher index, until transmission stops for lack of data.
TSTAT records whenever a TxBD ring is exhausted.
that are ready for transmission. If a non-ready TxBD is fetched from a ring, that ring is removed from
the scheduling pool until software re-enables it. Ready frames are repeatedly transmitted from a
chosen ring until its transmission quota is exhausted. The transmission quota for TxBD ring n is set
to WT n × 64 bytes, where WT n is a weight from the TR03WT/TR47WT registers. If a ring transmits
more data than its quota allows, the excess is deducted from its quota on the next transmission
opportunity, thereby preventing large frames from monopolizing the eTSEC bandwidth.
THLT2
TXF2
w1c
w1c
18
2
Table 15-15. TCTRL Field Descriptions (continued)
THLT3
TXF3
w1c
w1c
19
Figure 15-11. TSTAT Register Definition
3
THLT4
TXF4
w1c
w1c
20
4
THLT5
TXF5
w1c
w1c
21
5
All zeros
All zeros
THLT6
TXF6
w1c
w1c
Description
22
6
THLT7
TXF7
w1c
w1c
23
7
Enhanced Three-Speed Ethernet Controllers
Figure 15-11
24
8
describes the TSTAT
—
—
Access: w1c
15-37
15
31