MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 517

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

The timing parameters are summarized in
10.4.3.3.5
Allowance for slow output driver turn-off when reading NAND Flash EEPROMs is made via setting of
ORn[EHTR] and ORn[TRLX]. The extended read data hold time, shown at t
Figure
(requiring LALE assertion). LCSn is negated during t
time to disable their drivers.
10.4.3.4
Boot chip-select operation allows address decoding for a boot ROM before system initialization. LCS0 is
the boot chip-select output; its operation differs from other external chip-select outputs after a system reset.
Freescale Semiconductor
10-56, is a delay inserted by FCM between the last data read and another eLBC memory access
FCM Boot Chip-Select Operation
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
FCM Extended Read Hold Timing
1
Option Register
TRLX
In the parameters, SCY refers to a delay of OR n [SCY] clock cycles.
LCLK
(unused)
LALE
(unused)
LCS n
LFCLE/
LFALE
LFRE
LAD[0:7]
TA
Figure 10-56. FCM Read Data Timing with Extended Hold Time
0
0
1
1
Attributes
(for TRLX = 0, EHTR = 1, RST = 1, SCY = 1, CLKDIV = 4*N)
RST
Table 10-37. FCM Read Data Timing Parameters
0
1
0
1
Notes:
½+2×SCY
1+2×SCY
¾+SCY
1+SCY
t
RP
t
t
RC
EHTR
Table
Timing Parameter (LCLK Clock Cycles)
= Read data cycle time.
read cycle
= Extended read data hold time.
last read data
t
RC
t
10-37.
RHT
1
1
2
2
EHTR
2×SCY
2×SCY
SCY
SCY
t
to allow external devices and bus transceivers
WS
t
EHTR
3+2×SCY 8×(2+SCY)
3+2×SCY 8×(2+SCY)
2+SCY
2+SCY
t
RC
4×(2+SCY)
4×(2+SCY)
EHTR
1
t
WRT
Enhanced Local Bus Controller
in
Figure 10-45
and
10-69