MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 115

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
0x0_311C–
0x0_31FF
0x0_3110
0x0_3114
0x0_4500
0x0_4501
0x0_4502
0x0_4503
0x0_4504
0x0_4505
0x0_4506
0x0_4507
0x0_4510
0x0_4600
0x0_4601
0x0_4602
0x0_4603
0x0_4604
0x0_4605
Offset
I2C2DR—I
I2C2DFSRR—I
Reserved, should be cleared
URBR—ULCR[DLAB] = 0 UART1 receiver buffer register
UTHR—ULCR[DLAB] = 0 UART1 transmitter holding
register
UDLB—ULCR[DLAB] = 1 UART1 divisor least significant
byte register
UIER—ULCR[DLAB] = 0 UART1 interrupt enable register
UDMB—ULCR[DLAB] = 1 UART1 divisor most significant
byte register
UIIR—ULCR[DLAB] = 0 UART1 interrupt ID register
UFCR—ULCR[DLAB] = 0 UART1 FIFO control register
UAFR—ULCR[DLAB] = 1 UART1 alternate function
register
ULCR—ULCR[DLAB] = x UART1 line control register
UMCR—ULCR[DLAB] = x UART1 MODEM control register
ULSR—ULCR[DLAB] = x UART1 line status register
UMSR—ULCR[DLAB] = x UART1 MODEM status register
USCR—ULCR[DLAB] = x UART1 scratch register
UDSR—ULCR[DLAB] = x UART1 DMA status register
URBR—ULCR[DLAB] = 0 UART2 receiver buffer register
UTHR—ULCR[DLAB] = 0 UART2 transmitter holding
register
UDLB—ULCR[DLAB] = 1 UART2 divisor least significant
byte register
UIER—ULCR[DLAB] = 0 UART2 interrupt enable register
UDMB—ULCR[DLAB] = 1 UART2 divisor most significant
byte register
UIIR—ULCR[DLAB] = 0 UART2 interrupt ID register
UFCR—ULCR[DLAB] = 0 UART2 FIFO control register
UAFR—ULCR[DLAB] = 1 UART2 alternate function
register
ULCR—ULCR[DLAB] = x UART2 line control register
UMCR—ULCR[DLAB] = x UART2 MODEM control register
ULSR—ULCR[DLAB] = x UART2 line status register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
C2 data register
2
C2 digital filter sampling rate register
Register
Table 2-2. Memory Map (continued)
DUART
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
W
W
W
W
R
R
R
R
R
R
R
R
Reset
0x00
0x10
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x60
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x60
—
18.3.1.12/18-16
18.3.1.10/18-15
18.3.1.11/18-16
18.3.1.13/18-17
18.3.1.12/18-16
18.3.1.6/18-10
18.3.1.7/18-11
18.3.1.8/18-13
18.3.1.9/18-14
18.3.1.6/18-10
18.3.1.7/18-11
18.3.1.8/18-13
18.3.1.9/18-14
Section/Page
17.3.1.5/17-9
17.3.1.6/17-9
18.3.1.1/18-5
18.3.1.2/18-6
18.3.1.3/18-6
18.3.1.4/18-8
18.3.1.3/18-6
18.3.1.5/18-9
18.3.1.1/18-5
18.3.1.2/18-6
18.3.1.3/18-6
18.3.1.4/18-8
18.3.1.3/18-6
18.3.1.5/18-9
—
Memory Map
2-11