MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 835

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 15-116
15.5.3.10.7 Timer Counter Register (TMR_CNT_H/L)
The timer register (TMR_CNT_H/L) represents accurate time in terms clock ticks or in nano-seconds.
Writes to these registers will override the previous time. The register in eTSEC1 is shared for all eTSECs.
This is a read/write register. Figure 15-109 describes the definition for the TMR_CNT_H/L register.
Table 15-117
15.5.3.10.8 Timer Drift Compensation Addend Register (TMR_ADD)
Timer drift compensation addend register (TMR_ADD) is used to hold timer frequency compensation
value (FreqCompensationValue). The nominal frequency of the clock counter is determined by the
FreqDivRatio and the clock frequency (FreqClock). This register is programmed with 2
Frequency division ratio (FreqDivRatio) is the ratio between the frequency of the oscillator (TimerOsc)
and the desired clock frequency (NominalFreq). FreqDivRatio is a design constant chosen to be greater
than 1.0001. The ADDEND value is added to the 32-bit accumulator register at every rising edge of the
oscillator clock (TimerOsc). The clock counter is incremented at every carry pulse of the accumulator.
Freescale Semiconductor
Offset eTSEC1:0x2_4E18 (H); 0x2_4E1C (L)
Reset
26–31
0–25
0–63
Bits
Bits
W
R
0
STAT_VEC Timer general purpose status vector. It will store the 6-bit queue number generated by the filer. User
TMR_CNT_
Name
Name
—
H/L
describes the fields of the TMR_STAT register.
describes the fields of the TMR_CNT_H/L register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
to decode this status vector. For example, user can encode received PTP packet message types
(Sync, Delay_req, Follow_up, Delay_resp, Management) in the filer virtual queue field.
Value of the current time counter. Current time is calculated by adding TMROFF_H/L with the
TMR_CNT_H/L counter. This register can be written through the register writes.Writes to the
TMR_CNT_L register copies the written value into the shadow TMR_CNT_L register. Writes to the
TMR_CNT_H register copies the values written into the shadow TMR_CNT_H register. Contents of the
shadow registers are copied into the TMR_CNT_L and TMR_CNT_H registers following a write into
the TMR_CNT_H register. Writes to these registers have precedence over the timer increment. The
user must write to TMR_CNT_L register first.
Reads from the TMR_CNT_L register copies the entire 64-bit clock time of the read enable into the
TMR_CNT_H/L shadow registers. Read instruction from the TMR_CNT_H register reads the value
stored in the TMR_CNT_H shadow register. The user must read the TMR_CNT_L register first to get
correct 64-bit TMR_CNT_H/L counter values.
TMR_CNT_H
Table 15-117. TMR_CNT_H/L Register Field Descriptions
Table 15-116. TMR_STAT Register Field Descriptions
Figure 15-109. TMR_CNT_H Register Definition
All zeros
31 32
Description
Description
Enhanced Three-Speed Ethernet Controllers
TMR_CNT_L
32
Access: Read/Write
/FreqDivRatio.
15-117
63