MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 193

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

4.3.3.3.1
Examples for various clock modes are listed in
Freescale Semiconductor
12–13
14–15
16–18
19–21
22–27
30–31
9–11
Bits
6–7
28
29
0
1
2
3
4
5
8
BOOTSEQ
COREDIS
PCIHOST
ROMLOC
Reserved
Reserved
Reserved
Reserved
Reserved
TSEC1M
TSEC2M
PCIARB
RLEXT
SWEN
Name
LALE
BMS
TLE
CFG_RESET_SOURCE[0:3]
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
DDR controller clock (MHz)
Examples for Hard-Coded Reset Configuration Words Usage
Table 4-25. Examples For Hard-Coded Reset Configuration Words Usage
Core clock (MHz)
PCI_CLK (MHz)
Table 4-24. Hard-Coded Reset Configuration Word High Field Values
csb_clk (MHz)
CFG_RESET_SOURCE[0:3] = 1000–1100
1000
101
000
Field Values when
1001
011
101
000000
000
00
00
00
00
0
1
0
0
1
1
0
0
0
1000
133
266
266
33
1010
000
001
Table
1001
133
266
333
4-25.
66
1100
001
101
1010
PCI agent mode
External arbiter is used
e300 core is disabled (boot holdoff)
Boot memory space is 0xFF80_0000–
0xFFFF_FFFF. MSR[IP] initial value is 0b1.
Boot sequencer is disabled.
Software watchdog disabled.
Boot ROM interface location.
Legacy mode.
000 = MII mode
001 = RMII
011 = RGMII mode
101 = RTBI mode
Big-endian mode
Normal timing
167
333
250
33
1011
133
266
266
66
Reset, Clocking, and Initialization
Meaning
—
—
—
—
—
1100
167
333
333
33
4-27