MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 295

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Note the following:
PMC Wake-Up When the MPC8313E is a PCI Agent
This sequence assumes the device is a PCI agent in D3Warm state, with power supplied only by the VDDC
power rail. The VDD power rail has been externally switched to 0. Assume the PMC is set to wake on one
of the defined wake-up events and that the appropriate PMCMR[x] is set to 1. Assume that PME signaling
is desired and that PMCCR1[PME_EN] = 1.
Steps to wake up are as follows.
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5. Once all agents have transitioned appropriately the device may enter the D3Hot state. If the device
6. As host, the device transitions to D3Warm state by putting the e300 into deep sleep. This action
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1. A wake-up event occurs setting one of the PMCER[x] bits. The wake-up event will remain set in
2. In response to the wake-up event, PME signaling is generated asserting the PCI_PME signal to the
3. The PCI host recognizes the PCI_PME signal. The host may opt to leave the device in its current
wants to transition to the D3Warm state (power off a portion of the die) it must set the
PMCCR1[POWER_OFF] bit so that the EXT_PWR_CTRL signal will toggle, turning of the VDD
externally.
causes the qreq signal to be asserted which causes PMC to sequence in to D3Warm. If the
PMCCR1[POWER_OFF] bit is set the EXT_PWR_CTRL signal will transition low causing power
to be removed to a portion of the die.
In host mode, the PMCCR1[PME_EN] bit should be cleared. Also, the PMCCR1[USE_STATE]
bit should be cleared to indicate that the next_state and curr_state fields are ignored. The next_state
and curr_state fields in that register are NOT used in host mode. The curr_state field should be left
as 00.
When powering down in host mode, the e300 should ensure that the PMCER is cleared. Any
pending interrupt will prevent PMC from entering the low power state and asserting
EXT_PWR_CTRL.
Note that the next_state field in PMCCR1 is not writable by the e300. These bits are a reflection
of the values in the corresponding PCIPMR1[Power_State] field.
the PMCER[x] register until cleared by the e300.
Alternatively, the PCI host may request a change of state in the device through the PCI’s
PCIPMR1[Power_State] register, for example setting it to 00b (D0 mode). This state change will
be reflected into the PMC’s PMCCR1[NEXT_STATE] register field, and the wake-up flow would
continue at step 4.
host.
Note: In order for the device to assert PCI_PME, the PME_EN bit in the PCIPMR1 register must
be set to 1, AND the PMCCR1[PME_EN] bit must be set to 1.
state, in which case the sequence stops at this point. If the host decides to wake up the device, it
will change the power state field, PCIPMR1[Power_State] in the device PCI PME context block
to “00” (D0). This change will be reflected in the PMCCR1[NEXT_STATE] register bits in the
PMC module.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
System Configuration
5-87