MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 402

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
9.3.2.3
The debug signals MSRCID[0:4] and MDVAL have no function in normal DDR controller operation. A
detailed description of these signals can be found in
9.4
Table 9-5
In this table and in the register figures and field descriptions, the following access definitions apply:
9-8
Offset
0x10C
0x000
0x008
0x080
0x084
0x100
0x104
0x108
•
•
•
•
•
Signal
MCKE
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
CS0_BNDS—Chip select 0 memory bounds
CS1_BNDS—Chip select 1 memory bounds
CS0_CONFIG—Chip select 0 configuration
CS1_CONFIG—Chip select 1 configuration
TIMING_CFG_3—DDR SDRAM timing configuration 3
TIMING_CFG_0—DDR SDRAM timing configuration 0
TIMING_CFG_1—DDR SDRAM timing configuration 1
TIMING_CFG_2—DDR SDRAM timing configuration 2
Memory Map/Register Definition
shows the register memory map for the DDR memory controller.
Debug Signals
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
I/O
O
Clock enable. Output signals used as the clock enables to the SDRAM. MCKE can be negated to stop
clocking the DDR SDRAM. The MCKE signals should be connected to the same rank of memory as the
corresponding MCS and MODT signals. For example, MCKE[0] should be connected to the same rank of
memory as MCS[0] and MODT[0].
Meaning
Table 9-4. Clock Signals—Detailed Signal Descriptions (continued)
Timing Assertion/Negation—Asserted when DDR_SDRAM_CFG[MEM_EN] is set. Can be negated
State
Asserted—Clocking to the SDRAM is enabled.
Negated—Clocking to the SDRAM is disabled and the SDRAM should ignore signal transitions
High impedance—Always driven.
DDR Memory Controller—Block Base Address 0x0_2000
Table 9-5. DDR Memory Controller Memory Map
on MCK or MCK. MCK/MCK are don’t cares while MCKE is negated.
when entering dynamic power management or self refresh. Are asserted again when
exiting dynamic power management or self refresh.
Register
Section 5.4.3.8, “Debug
Description
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Configuration.”
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0011_0105
0x0000_0000
0x0000_0000
Reset
Freescale Semiconductor
Section/Page
9.4.1.2/9-10
9.4.1.2/9-10
9.4.1.3/9-11
9.4.1.4/9-12
9.4.1.5/9-14
9.4.1.6/9-16
9.4.1.1/9-9
9.4.1.1/9-9