MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 268

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
Table 5-61
5.7.5.5
Global timers counter registers (GTCNR1, GTCNR2, GTCNR3, and GTCNR4), shown in
four 16-bit, memory-mapped, read/write up-counters. A read cycle to a GTCNRn[CNV] fields yields the
current value of the appropriate timer but does not affect the counting operation. A write cycle to a
GTCNRn[CNV] field sets the register to the written value, causing its corresponding primary and
secondary prescaler counters to be reset.
Table 5-62
5.7.5.6
Global timers event registers (GTEVR1, GTEVR2, GTEVR3, and GTEVR4), shown in
used to report events recognized by any of the timers. On recognition of an output reference event, the
appropriate timer sets GTEVRn[REF], regardless of the corresponding GTMDRn[ORI]. The capture event
is only set if it is enabled by GTMDRn[CE]. GTEVRs appear as memory-mapped registers to users, which
can be read at any time.
GTEVRn bits are cleared by writing ones to them (writing zeros does not affect bit values). Both bits must
be reset before the timer negates the interrupt to the interrupt controller.
5-60
Offset
0–15
0–15
Bits
Bits
Reset
Offset 0x30(GTEVR1)
Reset
W
R
W
R
Name
0x1C(GTCNR1)
0x1E(GTCNR2)
Name
CNV
LCV
0x32(GTEVR2)
0
defines the bit fields of GTCPRn.
defines the bit fields of GTCNR.
0
Global Timers Counter Registers (GTCNR1–GTCNR4)
Global Timers Event Registers (GTEVR1–GTEVR4)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Latched counter value. Corresponding timer’s 16-bit latched value.
Counter value.
Corresponding timer’s 16-bit read/write up-counter value.
Figure 5-45. Global Timers Counter Registers (GTCNR1—GTCNR4)
Figure 5-46. Global Timers Event Registers (GTEVR1—GTEVR4)
0x2C(GTCNR3)
0x2E(GTCNR4)
0x34(GTEVR3)
0x36(GTEVR4)
Table 5-61. GTCPR n Bit Settings
Table 5-62. GTCNR Bit Settings
—
All zeros
All zeros
CNV
Description
Description
Freescale Semiconductor
Figure
13
Access: Read/Write
Figure
REF
Access: w1c
w1c
14
5-46, are
5-45, are
CAP
w1c
15
15