MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 571

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

12.3.8.2
This section describes the DMA status register. The status register reports various DMA conditions during
and after the DMA transfer. Writing a 1 to a specific set bit clears the bit.
fields.
Table 12-11
Freescale Semiconductor
Offset 0x104, 0x184, 0x204, 0x284
Reset
31–8
Bits
Bits
6–3
3
2
1
0
7
2
W
R
31
Name
Name
CTM
TEM
CC
CS
CB
TE
—
—
describes the DMASRn register.
DMA Status Register (DMASR n )
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Transfer error mask. This bit determines the DMA response in the event of a transfer error.
0 The DMA will halt when a transfer error occurs.
1 The DMA will complete the transfer regardless of whether a transfer error occurs.
Note: Regardless of the setting of TEM, if an error condition was detected during the DMA transfer, it will
Channel transfer mode.
0 Chaining mode
1 Direct mode
Channel continue. This bit applies only to chaining mode. Setting this bit indicates that the current
descriptor segment should be repeated. CC is cleared by the DMA once the repeat takes effect, so it only
causes a single repeat.
0 Normal chaining
1 DMACDAR is not loaded from DMANDAR, causing a repeat of the current descriptor segment
Channel start. A 0-to-1 transition occurring on this bit when the channel is not busy (SR[CB] bit is 0) will
start the DMA process. If the channel is busy and a 0-to-1 transition occurs, the DMA channel will restart
from a previous halt condition. A 1-to-0 transition when the channel is busy (CB bit is 1) will halt the DMA
process. Nothing happens if the channel is not busy and a 1-to-0 transition occurs. This bit is cleared by the
DMA at the end of a transfer.
Reserved
Transfer error. Set when there is an error condition during the DMA transfer.
Reserved
Channel busy. This bit indicates whether the channel is busy. It is cleared as a result of any of the following
conditions: an error or completion of the DMA transfer.
0 No DMA transfer is currently in progress
1 A DMA transfer is currently in progress
cause DMASR n [TE] to be set.
Table 12-10. DMAMR n Field Descriptions (continued)
Figure 12-11. DMA Status Register (DMASR n )
Table 12-11. DMASR n Field Descriptions
—
All zeros
Description
Description
Figure 12-11
8
TE
7
6
Ò
shows the DMASRn
3
Access: User Mixed
DMA/Messaging Unit
CB
2
EOSI EOCDI
1
12-11
0