MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1147

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

19.4.1.6
SPIRD, shown in
SPIE[NE] is set, the core can read SPIRD.
Table 19-9
19.4.1.6.1
In reverse data mode (SPMODE[REV] = 1) and regular data mode (SPMODE[REV] = 0) the data is
placed in the SPIRD after reception is completed as described below for character length of 8 bits
(SPMODE[LEN] = 7).
Freescale Semiconductor
Offset 0x036
Offset 0x034
Offset 0x036
Reset
Reset 1
Reset
0–31
Bits
W
W
W
R
R
R
0
0
0
Name
DATA
1
shows the field descriptions of the SPI receive data hold register.
1
SPI Receive Data Hold Register (SPIRD)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reverse Mode SPMODE[REV] Examples
Figure 19-13. Example SPMODE[REV] = 1 SPMODE[LEN] = 7 MSB Sent First
Figure 19-12. Example SPMODE[REV] = 0 SPMODE[LEN] = 7 LSB Sent First
Received data. These bits are the received data from the SPI bus.
1
Figure
1
1
19-11, is used to receive a character of data from the SPI channel. Each time
Figure 19-11. SPI Receive Data Hold Register Definition
1
Table 19-9. SPI Receive Data Hold Field Descriptions
—
1
1
1
1
—
1
1
1
1
15
All zeros
All zeros
DATA
MSB
1
16
Description
1
17
1
1
DATA
1
1
1
22
1
23
LSB
23
MSB
1
24
1
24
25
1
Serial Peripheral Interface
1
Access: Read-only
Access: Read-only
Access: Read-only
DATA
1
—
1
1
30
1
19-15
LSB
31
31
31
1