MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1006

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
Length in this error scenario. If the Mult field is greater than one, then the host controller will automatically
execute the value of Mult transactions. The host controller will not execute all Mult transactions if:
16.6.8.2
A client buffer request to an isochronous endpoint may span 1 to N micro-frames. When N is larger than
one, system software may have to use multiple iTDs to read or write data with the buffer (if N is larger
than eight, it must use more than one iTD).
Figure 16-48
periodic schedule (that is, the periodic frame list and a set of iTDs). On the right is the client description
of its request. The description includes a buffer base address plus additional annotations to identify which
portions of the buffer should be used with each bus transaction. In the middle is the iTD data structures
used by the system software to service the client request. Each iTD can be initialized to service up to 24
transactions, organized into eight groups of up to three transactions each. Each group maps to one
micro-frame's worth of transactions. The EHCI controller does not provide per-transaction results within
a micro-frame. It treats the per-micro-frame transactions as a single logical transfer. On the left is the host
controller’s frame list. System software establishes references from the appropriate locations in the frame
list to each of the appropriate iTDs. If the buffer is large, then system software can use a small set of iTDs
to service the entire buffer. System software can activate the transaction description records (contained in
each iTD) in any pattern required for the particular data stream.
16-78
•
•
The endpoint is an OUT and Transaction n Length goes to zero before all the Mult transactions
have executed (ran out of data), or
The endpoint is an IN and the endpoint delivers a short packet, or an error occurs on a transaction
before Mult transactions have been executed. The end of micro-frame may occur before all of the
transaction opportunities have been executed. When this happens, the transfer state of the transfer
description is advanced to reflect the progress that was made, the result written back to the iTD and
the host controller proceeds to processing the next micro-frame.
Software Operational Model for iTDs
illustrates the simple model of how a client buffer is mapped by system software to the
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor