MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1076

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.8.6.3
Error interrupts will be least frequent and should be placed last in the interrupt service routine.
16.9
The host mode operation of the USB DR module is nearly EHCI-compatible with few minor differences.
For the most part, the module conforms to the data structures and operations described in Section 3, “Data
Structures,” and Section 4, “Operational Model,” in the EHCI specification. The particulars of the
deviations occur in the following areas:
For the purposes of the DR implementing dual-role host/device controller with support for OTG
applications, it is necessary to deviate from the EHCI specification. Device operation and OTG operation
are not specified in the EHCI and thus the implementation supported in the DR module is proprietary.
16.9.1
The DR module supports directly connected full and low speed devices without requiring a companion
controller by including the capabilities of a USB 2.0 high speed hub transaction translator. Although there
is no separate transaction translator block in the system, the transaction translator function normally
associated with a high speed hub has been implemented within the DMA and Protocol engine blocks. The
embedded transaction translator function is an extension to EHCI interface, but makes use of the standard
16-148
USB Error Interrupt
System Error
•
•
•
Interrupt
Embedded transaction translator—Allows direct attachment of FS and LS devices in host mode
without the need for a companion controller.
Device operation—In host mode, the device operational registers are generally disabled and thus
device mode is mostly transparent when in host mode. However, there are a couple exceptions
documented in the following sections.
Embedded design interface—The module does not have a PCI interface and therefore the PCI
configuration registers described in the EHCI specification are not applicable.
Port Change
Sleep Enable (Suspend)
Reset Received
Deviations from the EHCI Specifications
Embedded Transaction Translator Function
Error Interrupts
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Interrupt
This error is redundant because it combines USB Interrupt and an error status in the dTD. The DCD
will more aptly handle packet-level errors by checking dTD status field upon receipt of USB Interrupt
(w/ ENDPTCOMPLETE).
Unrecoverable error. Immediate Reset of core; free transfers buffers in progress and restart the DCD.
Table 16-94. Low Frequency Interrupt Events
Change software state information.
Change software state information. Low power handling as necessary.
Change software state information. Abort pending transfers.
Table 16-95. Error Interrupt Events
Action
Action
Freescale Semiconductor