MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 399

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

9.3.2
The following sections describe the DDR SDRAM controller input and output signals, the meaning of their
different states, and relative timing information for assertion and negation.
9.3.2.1
Table 9-3
Freescale Semiconductor
MDQS[0:3]
MDQ[0:31]
Signal
describes the DDR controller memory interface signals.
Detailed Signal Descriptions
Memory Interface Signals
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
I/O
I/O Data bus. Both input and output signals on the DDR memory controller.
I/O Data strobes. Inputs with read data, outputs with write data.
O
O
I
I
Table 9-3. Memory Interface Signals—Detailed Signal Descriptions
As outputs, the data strobes are driven by the DDR memory controller during a write transaction. The
memory controller always drives these signals low unless a read has been issued and incoming data
strobes are expected. This keeps the data strobes from floating high when there are no transactions on
the DRAM interface.
As inputs, the data strobes are driven by the external DDR SDRAMs during a read transaction. The data
strobes are used by the memory controller to synchronize data latching.
As outputs for the bidirectional data bus, these signals operate as described below.
As inputs for the bidirectional data bus, these signals operate as described below.
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—Driven coincident with corresponding data strobes (MDQS) signal.
Timing Assertion/Negation—The DDR SDRAM drives data during a READ transaction.
Timing Assertion/Negation—If a WRITE command is registered at clock edge n , data strobes at the
Timing Assertion/Negation—If a READ command is registered at clock edge n , and the latency is
State
State
State
State
Asserted/Negated—Represent the value of data being driven by the DDR memory controller.
High impedance—No READ or WRITE command is in progress; data is not being driven by
Asserted/Negated—Represents the state of data being driven by the external DDR
High impedance—No READ or WRITE command in progress; data is not being driven by the
Asserted/Negated—Driven high when positive capture data is transmitted and driven low
Asserted/Negated—Driven high when positive capture data is received and driven low when
the memory controller or the DRAM.
SDRAMs.
memory controller or the DRAM.
when negative capture data is transmitted. Centered in the data “eye” for writes;
coincident with the data eye for reads. Treated as a clock. Data is valid when signals
toggle. See
DRAM assert centered in the data eye on clock edge n + 1. See the JEDEC DDR
SDRAM specification for more information.
negative capture data is received. Centered in the data eye for writes; coincident with
the data eye for reads. Treated as a clock. Data is valid when signals toggle. See
Table 9-24
programmed in TIMING_CFG_1[CASLAT] to be m clocks, data strobes at the DRAM
assert coincident with the data on clock edge n + m . See the JEDEC DDR SDRAM
specification for more information.
for byte lane assignments.
Table 9-24
for byte lane assignments.
Description
DDR Memory Controller
9-5