MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 510

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
The placement of ECC code words in relation to FMR[ECCM] is shown in
devices, only a single 512-byte main region is ECC-protected. For large-page devices, there are four
adjacent main regions, and each has a 16-byte spare region—of which only one is shown in the figure. If
eLBC is configured to generate ECC (BRn[DECC] = 10), FCM will substitute on full-page write transfers
the three code word bytes in place of the spare region data originally provided at the locations shown in
Figure 10-49
reference. Transfers shorter than a full page, however, require software to prepare the appropriate ECC in
the spare region. Similarly, FCM can check and correct bit errors on full-page reads if BRn[DECC] = 01
or 10. A correctable error is a single bit error in any 512-byte block of main region data, as judged by
comparison of a regenerated ECC with the ECC retrieved from the spare region, or a single bit error in the
retrieved ECC only. Bit errors in the main region are corrected before FCM completes its final read transfer
and signals an event in LTESR[CC]. The bit vector in LTECCR[SBCE] can be checked on FCM CC event
to find out if any 512-byte block or the corresponding ECC have single bit correctable errors. Errors that
appear more complex (two or more bits in error per 512-byte block) are not corrected, but are flagged as
parity errors by FCM. The bit vector in LTEATR[PB] or LTECCR[MBUE] can be checked to determine
which 512-byte blocks in a large-page NAND Flash main region were found to be uncorrectable.
10.4.3.2
FCM has a fully general command and data transfer sequencer that caters for both common and
specific/proprietary NAND Flash command sequences. The command sequencer reads a program out of
the FIR register, which can hold up to 8 instructions, each represented by a 4-bit op-code, as illustrated in
Figure
likewise to subsequent instructions, ending at FIR[OP7] or until the only instructions remaining are NOPs.
If FIR contains nothing but NOP instructions, FCM will not assert LCSn, otherwise, LCSn is asserted prior
to the first instruction and remains asserted until the last instruction has completed. If LTESR[CC] is
enabled, completion of the last instruction will trigger a command completion event interrupt from eLBC.
Prior to executing a sequence, necessary operands for the instructions will need to be set in the FMR, FCR,
MDR, FBCR, FBAR, and FPAR registers. The AS0–AS3 address and data pointers associated with FCM’s
use of MDR all reset to select AS0 at the start of the instruction sequence. A complete list of op-codes can
be found in
10-62
ECCM
0
1
10-50. The first instruction executed is read from FIR[OP0], the next is read from FIR[OP1], and
Byte 0
Figure 10-49. ECC Placement in NAND Flash Spare Regions in Relation to FMR[ECCM]
Section 10.3.1.18, “Flash Instruction Register (FIR).”
Programming FCM
and write the same 24-bit ECC code in the appropriate FECC
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Main Region
Main Region
Byte 511 Other Mains Spare 0
—
—
5
EC0 EC1 EC2
6
7
EC0 EC1 EC2
8
9
n
Figure
register for software
10
11
10-49. For small-page
Freescale Semiconductor
—
12
—
13
14
15