MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 652

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
14.3
The host processor maintains a record of current secure sessions and the corresponding keys and contexts
of those sessions. Once the host has determined that a security operation is required, it creates a
‘descriptor’ containing all the information the SEC needs to perform the security operation. The host
creates the descriptor in main memory, then writes a pointer to the descriptor into the fetch FIFO of the
SEC channel. The channel uses this pointer to read the descriptor into its descriptor buffer. Once it obtains
the descriptor, the SEC uses its bus mastering capability to obtain inputs and write results, thus off-loading
data movement and encryption operations from the host processor.
For test purposes, it is also possible for the host to write keys, context, and text-data directly to execution
units, using the SEC’s host-controlled access. This method avoids use of descriptors.
14.3.1
SEC descriptors are conceptually similar to descriptors used by most devices with DMA capability. The
descriptors have a fixed length of 64 bytes, that is, eight long-words, consisting of one ‘header dword’ and
seven ‘pointer dwords.’ See
14-10
0x3_4800–0x3_4FFF AESU FIFO
0x3_6800–0x3_6FFF MDEU FIFO
0x3_6400–0x3_647F MDEU key memory registers
0x3_4100–0x3_4108 AESU context memory registers
0x3_4400–0x3_4408 AESU key memory registers
0x3_6100–0x3_6120 MDEU context memory registers
Address Offset
(AD 17–0)
0x3_4050
0x3_6000
0x3_6008
0x3_6010
0x3_6018
0x3_6028
0x3_6030
0x3_6038
0x3_6040
0x3_6050
Descriptor Overview
Descriptor Structure
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
AESUEMR—AESU end-of-message register
MDEUMR—MDEU mode register
MDEUKSR—MDEU key size register (bytes)
MDEUDSR—MDEU data size register (bits)
MDEURCR—MDEU reset control register
MDEUSR—MDEU status register
MDEUISR—MDEU interrupt status register
MDEUICR—MDEU interrupt control register
MDEU ICV size register
MDEUEMR—MDEU end-of-message register
Figure 14-3
Table 14-3. SEC Address Map (continued)
Register
for the descriptor format.
MDEU
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
R
R
Access
Word
Word
Word
Word
Word
Word
By
Freescale Semiconductor
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