MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1165

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.2, 10-4
10.3.1.1, 10-10
10.3.1.2, 10-12
10.3.1.2.1, 10-12
10.3.1.7, 10-24
10.3.1.9, 10-26
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
In UPM mode, LGPL2 is one of six general purpose signals; it is driven with a
value programmed into the UPM array.
LFRE enables data read cycles from NAND Flash EEPROMs controlled by FCM.
In the LGPL3/LFWP row, changed the first sentence in the State Meaning to read:
Asserted/Negated—In UPM mode, LGPL3 is one of six general purpose signals;
it is driven with a value programmed into the UPM array.
In Table 10-2, LBCTL signal, changed the first sentence in the signal description
to the following:
The memory controller activates LBCTL for the local bus when a GPCM-, UPM-,
or FCM-controlled bank is accessed.
For the LA[0:25] signal, changed the State Meaning to read:
Asserted/Negated—LA is the address bus used to transmit addresses to external
RAM devices. Refer to Section 10.5, “Initialization/Application Information,” for
address signal multiplexing.
In Table 10-4, bits 19–20, replaced the second sentence in the description to:
For BR0, PS is configured from the field in reset configuration word as loaded
during reset.
Second paragraph, changed to the following:
The ORn registers are interpreted differently depending on which of the three
machine types is selected for that bank. Because bank 0 can be used to boot, the
reset value of OR0 may be different depending on power-on configuration
options. Table 10-4 shows the reset values for OR0.
Moved Table 10-6 under Section 10.3.1.2, following the second paragraph and
renumbered as Table 10-4. Renumbered the following tables.
In the first paragraph, fourth sentence and on, replaced text with:
To avoid race conditions between software and a busy eLBC, registers that affect
currently running special operation and LSOR must not be re-written before a
pending special operation has been completed. The UPM and FCM have different
indications of when such special operations are completed. The behavior of eLBC
is unpredictable if special operation modes are altered between LSOR being
written and the relevant memory controller completing that access.
Replaced the first paragraph, bullets, and second paragraph with the following:
The transfer error status register (LTESR) indicates the cause of an error or event.
LTESR, shown in Figure 10-13, is a write-1-to-clear register. Reading LTESR
occurs normally; however, write operations can clear but not set bits. A bit is
cleared whenever the register is written, and the data in the corresponding bit
location is a 1. For example, to clear only the write protect error bit (LTESR[WP])
without affecting other LTESR bits, 0x0400_0000 should be written to the
register. After any error/event reported by LTESR, LTEATR[V] must be cleared
for LTESR to updated again.
Revision History
A-7