MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 772

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.3.5
The RBIFX register provides a set of four 6-bit offsets for locating up to four octets in a received frame
and passing them to the receive queue filer as the user-defined ARB property. Through RBIFX a custom
ARB filer property can be constructed from arbitrary bytes, which allows frame filing on the basis of
bitfields not ordinarily provided to the filer, such as bits from the Ethernet preamble or TCP flags. The
value of property ARB is the concatenation of {B0, B1, B2, B3} to 32-bits, where B0–B3 are the bytes as
defined by RBIFX.
Table 15-31
15-54
Offset eTSEC1:0x2_4330; eTSEC2:0x2_5330
Reset
Figure 15-26
\
Bits
Bits
0–1
2–7
29
30
31
W
R
B0CTL
0
Name
B0OFFSET Offset relative to the header defined by B0CTL that locates byte 0 of property ARB. An effective offset
EN5
EN6
EN7
1
B0CTL
Name
describes the RBIFX register.
2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Receive Bit Field Extract Control Register (RBIFX)
Receive queue 5 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 6 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 7 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
describes the definition for the RBIFX register.
B0OFFSET
Location of byte 0 of property ARB.
00 Byte 0 is not extracted, and appears as zero in property ARB.
01 Byte 0 is located in the received frame at offset (B0OFFSET – 8) bytes from the first byte of the
10 Byte 0 is located in the received frame at offset B0OFFSET bytes from the byte after the last byte of
11 Byte 0 is located in the received frame at offset B0OFFSET bytes from the byte after the last byte of
of zero points to the first byte of the specified header.
Ethernet DA. In non-FIFO modes, a negative effective offset points to bytes of the standard Ethernet
preamble. Values of B0OFFSET less than 8 are reserved in FIFO modes.
the layer 2 header.
the layer 3 header.
Table 15-30. RQUEUE Field Descriptions (continued)
7
B1CTL
8
Figure 15-26. RBIFX Register Definition
Table 15-31. RBIFX Field Descriptions
9
10
B1OFFSET
All zeros
15 16
Description
B2CTL
Description
17 18
B2OFFSET
23 24
B3CTL
Freescale Semiconductor
25 26
Access: Read/Write
B3OFFSET
31