MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 478

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
Table 10-19
10.3.1.13 Transfer Error Address Register (LTEAR)
The transfer error address register (LTEAR) captures the address of a transaction that caused an
error/event. The transfer error address register (LTEAR) is shown in
Table 10-20
10.3.1.14 Transfer Error ECC Register (LTECCR)
The transfer error ECC register (LTECCR) captures single bit and multibit errors per 512-byte sector in
FCM mode. LTECCR, shown in
not set bits. It captures the errors during full page read transfers on FCM command completion event,
provided ECC check is enabled in BRx[DECC].
10-30
11–15
16–19
20–23
24–30
4–10
Offset 0x0_50C0
0–31
Reset
Bits
Bits
0–2
31
3
W
R
0
SRCID Captures the source of the transaction when this information is provided on the internal interface to the eLBC.
Name
Name
RWB
BNK
PB
—
—
—
V
A
describes LTEATR fields.
describes LTEAR fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Transaction type for the error:
0 The transaction for the error was a write transaction.
1 The transaction for the error was a read transaction.
Reserved
Error on block for FCM. For FCM, there are at most four 512-byte page blocks (for a large page device)
checked by ECC. A bit is set for the 512-byte block that had an uncorrectable ECC error on read (bit 16
represents block 0, the first 512 bytes of a page; if ORx[PGS] = 0, bits 17–19 are always 0).
Memory controller bank. There is one error status bit per memory controller bank (bit 20 represents bank 0).
A bit is set for the local bus memory controller bank that had an error.
Reserved
Error attribute capture is valid. Indicates that the captured error information is valid.
0 Captured error attributes and address are not valid.
1 Captured error attributes and address are valid.
Transaction address for the error. For GPCM and UPM, holds the 32-bit address of the transaction resulting
in an error. For FCM, this register is undefined.
Figure 10-17. Transfer Error Address Register (LTEAR)
Figure
Table 10-19. LTEATR Field Descriptions
Table 10-20. LTEAR Field Descriptions
10-18, is a write-1-to-clear register. Write operations can clear but
All zeros
Description
Description
A
Figure
10-17.
Freescale Semiconductor
Access: Read/Write
31