MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 974

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
ascertain the capabilities of the module, and control the module’s operation. It also has registers to control
snoopability and priority of the DMA interface.
16.4.2
The module contains a local DMA engine. The DMA engine interfaces internally to the CSB. It is
responsible for moving all of the data to be transferred over the USB between the module and buffers in
system memory. Like the system interface block, the DMA engine block uses a simple synchronous bus
signaling protocol that eases connections to a number of different standard buses.
The DMA controller must access both control information and packet data from system memory. The
control information is contained in link list–based queue structures. The DMA controller has state
machines that are able to parse data structures defined in the EHCI specification. In host mode, the data
structures are EHCI compliant and represent queues of transfers to be performed by the host controller,
including the split-transaction requests that allow an EHCI controller to direct packets to FS and LS
devices. In device mode, the data structures are designed to be similar to those in the EHCI specification
and are used to allow device responses to be queued for each of the active pipes in the device.
16.4.3
The FIFO RAM controller is used for context information and to control FIFOs between the protocol
engine and the DMA controller. These FIFOs decouple the system processor/memory bus requests from
the extremely tight timing required by USB.
The use of the FIFO buffers differs between host and device mode operation. In host mode, a single data
channel is maintained in each direction through the buffer memory. In device mode, multiple FIFO
channels are maintained for each of the active endpoints in the system.
In host mode, the USB DR module uses a 512-byte Tx buffer and a 512-byte Rx buffer. Device operation
uses a single 512-byte Rx buffer and a 512-byte Tx buffer for each endpoint. The 512-byte buffers allow
the module to buffer a complete HS bulk packet.
16.4.4
The USB DR module interfaces to any UTMI- or ULPI-compatible PHY. The primary function of the port
controller block is to isolate the rest of the module from the transceiver, and to move all of the transceiver
signaling into the primary clock domain of the module. This allows the module to run synchronously with
the system processor and its associated resources.
Due to pincount limitations the module only supports certain combinations of PHY interfaces and USB
functionality. Refer to
16-46
DMA Engine
FIFO RAM Controller
PHY Interface
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 16-38
Table 16-38. Supported PHY Interfaces
for more information.
UTMI
ULPI
PHY
Host/Device/OTG
Host/Device
Function
Freescale Semiconductor