MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 221

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

5.2.4.8
The DDR local access window n attributes registers (DDRLAWAR0
Figure
Table 5-17
5.2.4.8.1
The core may use a DDR SDRAM device to fetch its boot vector. For this purpose an 8-Mbyte (2
local access window is defined by DDRLAWBAR0[SIZE] reset value, and DDRLAWAR0 is enabled
according to the value set in the reset configuration word high ROMLOC and RLEXT field.
Freescale Semiconductor
1
2
26–31
1–25
‘
Bits
The reset value of DDRLAWAR0[EN] depends on the reset configuration word high values. See
“DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value,”
The reset value of DDRLAWAR0[SIZE] is always 0b010110, meaning an 8-Mbyte local access window. See
“DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value,”
Offset 0xA4
Reset
0
W
R
5-9.
Figure 5-9. DDR Local Access Window n Attributes Registers (DDRLAWAR0–DDRLAWAR1)
0xAC
Name
EN
SIZE
0
EN
—
defines the bit fields of DDRLAWAR0–DDRLAWAR1.
1
DDR Local Access Window n Attributes Registers
(DDRLAWAR0–DDRLAWAR1)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value
0 The DDR local access window n is disabled.
1 The DDR local access window n is enabled and other DDRLAWAR n and DDRLAWBAR n fields combine
Reserved. Write has no effect, read returns 0.
Identifies the size of the window from the starting address. Window size is 2
000000–001010 Reserved. Window is undefined.
001011 4 Kbytes
001100 8 Kbytes
001101 16 Kbytes
. . . . . . . 2
011110 2 Gbytes
011111–111111 Reserved. Window is undefined.
to identify an address range for this window.
(SIZE+1)
Table 5-17. DDRLAWAR0–DDRLAWAR1 Bit Settings
bytes
—
for a detailed description.
for a detailed description.
All zeros
Description
1,2
–
DDRLAWAR1) are shown in
(SIZE+1)
Section 5.2.4.8.1,
bytes.
25 26
System Configuration
Access: Read/Write
Section 5.2.4.8.1,
SIZE
(22+1)
5-13
)
31