MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 491

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.4.1.3
The three memory controllers in the eLBC generate an internal transfer acknowledge signal, TA, to allow
data on LAD to be either sampled (for reads) or changed (on writes). The data sampling/data change
always occurs at the end of the bus cycle in which the eLBC asserts TA internally. In eLBC debug mode,
TA is also visible externally on the LDVAL pin. The GPCM controller automatically generates TA
according to the timing parameters programmed for them in the option and mode registers; FCM generates
TA whenever data read and write instructions are executed out of register FIR; a UPM generates TA only
when a UPM pattern has the UTA RAM word bit set.
Note that TA and LALE are never asserted together, and that for the duration of LALE, LCSn (or any other
control signal) remains negated or frozen.
Freescale Semiconductor
LA[21:25]
LCLK
LALE
LCS n
LWE
LAD[0:7]
LAD[8:31]
Figure 10-30. Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420 (LCRR[PBYP] = 0)
Data Transfer Acknowledge (TA)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Note: All address and signal values are shown in hexadecimal.
00
54
20
Figure 10-31. Basic eLBC Bus Cycle with LALE, TA, and LCS n
00
D(B
D(Bk) = k
LCLK
LCS n
0
LALE
)
LAD
TA
00
54
21
th
of 32 data bytes
01
D(B
Address
1
)
00
54
22
02
D(B
2
)
Figure 10-31
Data
03
00
54
23
1C
54
3D
shows LALE, TA (internal), and LCSn.
00
1D
D(B
29
)
54
3E
00
Enhanced Local Bus Controller
1E
D(B
30
)
00
54
3F
1F
D(B
31
)
10-43