MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 975

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.5
Host Data Structures
This section defines the interface data structures used to communicate control, status, and data between
HCD (software) and the Enhanced Host Controller (hardware). The data structure definitions in this
section support a 32-bit memory buffer address space. The interface consists of a periodic schedule,
periodic frame list, asynchronous schedule, isochronous transaction descriptors, split-transaction
isochronous transfer descriptors, queue heads, and queue element transfer descriptors.
The periodic frame list is the root of all periodic (isochronous and interrupt transfer type) support for the
host controller interface. The asynchronous list is the root for all the bulk and control transfer type support.
Isochronous data streams are managed using isochronous transaction descriptors. Isochronous
split-transaction data streams are managed with split-transaction isochronous transfer descriptors. All
interrupt, control, and bulk data streams are managed with queue heads and queue element transfer
descriptors. These data structures are optimized to reduce the total memory footprint of the schedule and
to reduce (on average) the number of memory accesses needed to execute a USB transaction.
Note that software must ensure that no interface data structure reachable by the EHCI host controller spans
a 4K-page boundary.
The data structures defined in this section are (from the host controller’s perspective) a mix of read-only
and read/writable fields. The host controller must preserve the read-only fields on all data structure writes.
16.5.1
Periodic Frame List
Figure 16-35
shows the organization of the periodic schedule. This schedule is for all periodic transfers
(isochronous and interrupt). The periodic schedule is referenced from the operational registers space using
the PERIODICLISTBASE address register and the FRINDEX register. The periodic schedule is based on
an array of pointers called the periodic frame list. The PERIODICLISTBASE address register is combined
with the FRINDEX register to produce a memory pointer into the frame list. The periodic frame list
implements a sliding window of work over time.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
16-47