MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 54

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Figure
Number
17-11
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
18-16
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
20-1
21-1
21-2
21-3
21-4
21-5
21-6
21-7
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Example I
UART Block Diagram .......................................................................................................... 18-2
Receiver Buffer Registers (URBR1 and URBR2) ................................................................ 18-6
Transmitter Holding Registers (UTHR1 and UTHR2) ......................................................... 18-6
Divisor Most Significant Byte Registers (UDMB1 and UDMB2) ....................................... 18-7
Divisor Least Significant Byte Registers (UDLB1 and UDLB2)......................................... 18-7
Interrupt Enable Registers (UIER1 and UIER2)................................................................... 18-8
Interrupt ID Registers (UIIR1 and UIIR2)............................................................................ 18-9
FIFO Control Registers (UFCR1 and UFCR2)................................................................... 18-11
Line Control Register (ULCR1 and ULCR2) ..................................................................... 18-12
Modem Control Register (UMCR1 and UMCR2).............................................................. 18-13
Line Status Register (ULSR1 and ULSR2) ........................................................................ 18-14
Modem Status Register (UMSR1 and UMSR2) ................................................................. 18-15
Scratch Register (USCR) .................................................................................................... 18-16
Alternate Function Register (UAFR) .................................................................................. 18-16
DMA Status Register (UDSR) ............................................................................................ 18-17
UART Bus Interface Transaction Protocol Example .......................................................... 18-19
SPI Block Diagram ............................................................................................................... 19-2
Single-Master/Multi-Slave Configuration ............................................................................ 19-4
Multiple-Master Configuration ............................................................................................. 19-6
SPMODE-SPI Mode Register Definition ............................................................................. 19-9
SPI Transfer Format with SPMODE[CP] = 0..................................................................... 19-11
SPI Transfer Format with SPMODE[CP] = 1..................................................................... 19-11
SPIE—SPI Event Register Definition................................................................................. 19-12
SPIM—SPI Mask Register Definition................................................................................ 19-13
SPI Command Register Definition ..................................................................................... 19-14
SPI Transmit Data Hold Register Definition ...................................................................... 19-14
SPI Receive Data Hold Register Definition........................................................................ 19-15
Example SPMODE[REV] = 0 SPMODE[LEN] = 7 LSB Sent First.................................. 19-15
Example SPMODE[REV] = 1 SPMODE[LEN] = 7 MSB Sent First................................. 19-15
Example SPMODE[REV] = 1 SPMODE[LEN] = 15 MSB Sent First............................... 19-16
Example SPMODE[REV] = 0 SPMODE[LEN] = 15 LSB Sent First................................ 19-16
JTAG Interface Block Diagram ............................................................................................ 20-1
GPIO Module Block Diagram .............................................................................................. 21-1
GPIO Direction Register (GPDIR) ....................................................................................... 21-3
GPIO Open Drain Register (GPODR) .................................................................................. 21-3
GPIO Data Register (GPDAT) .............................................................................................. 21-4
GPIO Interrupt Event Register (GPIER) .............................................................................. 21-4
GPIO Interrupt Mask Register (GPIMR).............................................................................. 21-5
GPIO Interrupt Control Register (GPICR) ........................................................................... 21-5
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
C Interrupt Service Routine Flowchart ............................................................. 17-20
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Freescale Semiconductor
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