MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 459

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.3.1.2
The OR
the following three modes of operation as defined by BRn[MSEL]:
The OR
that bank. Because bank 0 can be used to boot, the reset value of OR0 may be different depending on
power-on configuration options.
Freescale Semiconductor
24–26
28–29
Bits
27
30
31
•
•
•
GPCM mode
FCM mode
UPM mode
n
n
Name
MSEL Machine select. Specifies the machine to use for handling memory operations.
ATOM Atomic operation. Writes (reads) to the address space handled by the memory controller bank reserve the
registers are interpreted differently depending on which of the three machine types is selected for
registers define the sizes of memory banks and access attributes. The ORn attribute bits support
—
—
V
Option Registers (OR0–OR3)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
000 GPCM (possible reset value)
001 FCM (possible reset value)
010 Reserved
011 Reserved
100 UPMA
101 UPMB
110 UPMC
111 Reserved
Reserved
selected memory bank for the exclusive use of the accessing device. The reservation is released when the
device performs a read (write) operation to this memory controller bank. If a subsequent read (write) request
to this memory controller bank is not detected within 256 bus clock cycles of the last write (read), the
reservation is released and an atomic error is reported (if enabled).
00 The address space controlled by this bank is not used for atomic operations.
01 Read-after-write-atomic (RAWA).
10 Write-after-read-atomic (WARA).
11 Reserved
Reserved
Valid bit. Indicates that the contents of the BR n and OR n pair are valid. LCS n does not assert unless V is set
(an access to a region that has no valid bit set may cause a bus time-out). After a system reset, only BR0[V]
is set.
0 This bank is invalid.
1 This bank is valid.
eLBC not used as a boot source
FCM (small page NAND Flash)
FCM (large page NAND Flash)
Table 10-4. BR
Boot Source
GPCM
Table 10-5
Table 10-5. Reset value of OR0 Register
n
shows the reset values for OR0.
Field Descriptions (continued)
Description
OR0 Reset Value
0000_03AE
0000_07AE
0000_0FF7
0000_0F07
Enhanced Local Bus Controller
10-11