MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 213

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

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Freescale Semiconductor
Local Memory
Offset (Hex)
Depends on reset configuration word high values. See
Depends on reset configuration word high values. See
for details.
Depends on reset configuration word high values. See
details.
Depends on reset configuration word high values. See
details.
Depends on reset configuration word high values. See
Value,”
Depends on reset configuration word high values. See
details.
Depends on reset configuration word high values. See
Value,”
0x0_00B0–
0x0_0040–
0x0_0070–
0x0_002C
0x0_003C
0x0_005C
0x0_006C
0x0_009C
0x0_00A0
0x0_00A4
0x0_00A8
0x0_00AC
0x0_00FC
0x0_0024
0x0_0028
0x0_0030
0x0_0034
0x0_0038
0x0_0060
0x0_0064
0x0_0068
for details.
for details.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
eLBC local access window 0 attribute register (LBLAWAR0)
eLBC local access window 1 base address register (LBLAWBAR1)
eLBC local access window 1 attribute register (LBLAWAR1)
eLBC local access window 2 base address register (LBLAWBAR2)
eLBC local access window 2 attribute register (LBLAWAR2)
eLBC local access window 3 base address register (LBLAWBAR3)
eLBC local access window 3 attribute register (LBLAWAR3)
Reserved
PCI local access window 0 base address register (PCILAWBAR0)
PCI local access window 0 attribute register (PCILAWAR0)
PCI local access window 1 base address register (PCILAWBAR1)
PCI local access window 1 attribute register (PCILAWAR1)
Reserved
DDR local access window 0 base address register
(DDRLAWBAR0)
DDR local access window 0 attribute register (DDRLAWAR0)
DDR local access window 1 base address register
(DDRLAWBAR1)
DDR local access window 1 attribute register (DDRLAWAR1)
Reserved
Table 5-4. Local Access Register Memory Map (continued)
Register
Section 5.2.4.4.1, “LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value,”
Section 5.2.4.3.1, “LBLAWBAR0[BASE_ADDR] Reset Value,”
Section 5.2.4.5.1, “PCILAWBAR0[BASE_ADDR] Reset Value,”
Section 5.2.4.7.1, “DDRLAWBAR0[BASE_ADDR] Reset Value,”
Section 5.2.4.6.1, “PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset
Section 5.2.4.7.1, “DDRLAWBAR0[BASE_ADDR] Reset Value,”
Section 5.2.4.8.1, “DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
—
System Configuration
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Section/Page
5.2.4.5/5-10
5.2.4.6/5-11
5.2.4.5/5-10
5.2.4.6/5-11
5.2.4.7/5-12
5.2.4.8/5-13
5.2.4.7/5-12
5.2.4.8/5-13
5.2.4.4/5-9
5.2.4.3/5-8
5.2.4.4/5-9
5.2.4.3/5-8
5.2.4.4/5-9
5.2.4.3/5-8
5.2.4.4/5-9
for details.
—
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—
for
for
for
5-5