MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 136

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
[15:19]
Bit(s)
10
11
12
13
14
20
0
1
2
3
4
5
6
7
8
9
VXSNAN
/
VXZDZ
VXIMZ
Name
VXVC
MPC556
VXISI
VXIDI
FPRF
FEX
OX
VX
UX
XX
FR
FX
ZX
FI
—
Floating-point exception summary. Every floating-point instruction implicitly sets FPSCR[FX] if
that instruction causes any of the floating-point exception bits in the FPSCR to change from 0 to
1. The mcrfs instruction implicitly clears FPSCR[FX] if the FPSCR field containing FPSCR[FX]
is copied. The mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions can set or clear FPSCR[FX] ex-
plicitly. This is a sticky bit.
Floating-point enabled exception summary. This bit signals the occurrence of any of the enabled
exception conditions. It is the logical OR of all the floating-point exception bits masked with their
respective enable bits. The mcrfs instruction implicitly clears FPSCR[FEX] if the result of the log-
ical OR described above becomes zero. The mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions can-
not set or clear FPSCR[FEX] explicitly. This is not a sticky bit.
Floating-point invalid operation exception summary. This bit signals the occurrence of any invalid
operation exception. It is the logical OR of all of the invalid operation exceptions. The mcrfs in-
struction implicitly clears FPSCR[VX] if the result of the logical OR described above becomes ze-
ro. The mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot set or clear FPSCR[VX] explicitly.
This is not a sticky bit.
Floating-point overflow exception. This is a sticky bit.
Floating-point underflow exception. This is a sticky bit.
Floating-point zero divide exception. This is a sticky bit.
Floating-point inexact exception. This is a sticky bit.
Floating-point invalid operation exception for ×-×. This is a sticky bit.
Floating-point invalid operation exception for ×/×. This is a sticky bit.
Floating-point invalid operation exception for 0/0. This is a sticky bit.
Floating-point invalid operation exception for ×*0. This is a sticky bit.
Floating-point invalid operation exception for invalid compare. This is a sticky bit.
Floating-point fraction rounded. The last floating-point instruction that potentially rounded the in-
termediate result incremented the fraction. This bit is not sticky.
Floating-point fraction inexact. The last floating-point instruction that potentially rounded the in-
termediate result produced an inexact fraction or a disabled exponent overflow. This bit is not
sticky.
Floating-point result flags. This field is based on the value placed into the target register even if
that value is undefined. Refer to
15
16–19
Reserved
Floating-point invalid operation exception for SNaN. This is a sticky bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 3-5 FPSCR Bit Descriptions
Floating-point result class descriptor (C). Floating-point instructions other than the
compare instructions may set this bit with the FPCC bits, to indicate the class of the
result.
Floating-point condition code (FPCC). Floating-point compare instructions always
set one of the FPCC bits to one and the other three FPCC bits to zero. Other
floating-point instructions may set the FPCC bits with the C bit, to indicate the class
of the result. Note that in this case the high-order three bits of the FPCC retain their
relational significance indicating that the value is less than, greater than, or equal to
zero.
16
17
18
19
Floating-point less than or negative (FL or <)
Floating-point greater than or positive (FG or >)
Floating-point equal or zero (FE or =)
Floating-point unordered or NaN (FU or ?)
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
Table 3-6
Description
for specific bit descriptions.
MOTOROLA
3-14