MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 180

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

4.3.2 Model Limitations
4.3.3 Vocabulary Based Instruction Compression Algorithm
MPC555
USER’S MANUAL
No address arithmetic is allowed, because the address map changes during compres-
sion and no software tool can identify address arithmetic structures in the code.
The code compression algorithm is based on creating vocabularies of frequently
appearing PowerPC RISC instructions or instruction halves and replacing these
instructions with pointers to the vocabularies.
Compressed and bypass field lengths may vary. An example of compressed code is
shown in
Compression of the instructions in a vocabulary may be in one of the following modes.
• Slight changes in the core and existing RISC development tools — compilers,
• Compressed address space is up to four Megabytes (4 Mbytes).
• Branch displacement from its target:
1. Compression of the whole instruction into four vocabulary byte pointers. The
2. Compression of a combination of the instruction’s bytes into vocabulary point-
3. Bypass of the whole instruction. No compaction permitted.
/
simulators, manually coded libraries.
— Conditional branch displacement is up to two Kbytes (2 Kbytes).
— Unconditional branch displacement is up to two Mbytes (2 Mbytes).
MPC556
four compacted bytes may start on any bit location. Four of the decoded bits
and another bit for starting from the left or right side of the address location de-
termine the bit location for the byte start
ers and bypass of the other byte(s). Bypass is the placing of the field’s uncom-
pressed instruction information into the compressed code.
Figure
Branch displacement is hardware limited. The compiler can enlarge
the branch scope by creating branch chains.
4-2.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
BURST BUFFER
NOTE
MOTOROLA
4-4