MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 333

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.5.7.5 Transfer Size
9.5.7.6 Address Types
MPC555
USER’S MANUAL
The transfer size signals (TSIZ[0:1]) indicate the size of the requested data transfer.
During each transfer, the TSIZ signals indicate how many bytes are remaining to be
transferred by the transaction. The TSIZ signals can be used with BURST and AD-
DR[30:31] to determine which byte lanes of the data bus are involved in the transfer.
For nonburst transfers, the TSIZ signals specify the number of bytes starting from the
byte location addressed by ADDR[30:31]. In burst transfers, the value of TSIZ is al-
ways 00.
The address type (AT[0:3]), program trace (PTR), and reservation transfer (RSV) sig-
nals are outputs that indicate one of 16 address types. These types are designated as
either a normal or alternate master cycle, user or supervisor, and instruction or data
type. The address type signals are valid at the rising edge of the clock in which the
special transfer start (STS) signal is asserted.
A special use of the PTR and RSV signals is for the reservation protocol described in
9.5.9 Storage
tion on show cycles.
Table 9-7
definitions achieved by combining these pins.
/
MPC556
summarizes the pins used to define the address type.
Reservation. Refer to
Freescale Semiconductor, Inc.
Asserted
Negated
Negated
Negated
Negated
BURST
For More Information On This Product,
Table 9-6 BURST/TSIZE Encoding
RSV
STS
PTR
AT0
AT1
AT2
AT3
Pin
TS
Table 9-7 Address Type Pins
EXTERNAL BUS INTERFACE
Go to: www.freescale.com
Rev. 15 October 2000
0 = Special transfer
1 = Normal transfer
0 = Start of transfer
1 = No transfer
Must equal zero on MPC555 / MPC556
0 = Supervisor mode
1 = User mode
0 = Instruction
1 = Data
Reservation/Program Trace
0 = Program trace
1 = No program trace
0 = Reservation data
1 = No reservation
TSIZ(0:1)
01
10
11
00
00
9.5.13 Show Cycle Transactions
Function
Burst (16 bytes)
Transfer Size
Half-word
Word
Byte
x
Table 9-8
for informa-
MOTOROLA
lists all the
9-37